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2023-03-01arm: mvebu: Add support for generating PEX kwbimagePali Rohár
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_PEX which instruct make to generate kwbimage with PEX header. This image is used for booting from PCI Express device which is in the Root Complex mode. Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then start executing U-Boot proper. Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: Add support for generating NAND kwbimagePali Rohár
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct make to generate kwbimage with NAND header. This image is used for booting from NAND flash (either SPI or parallel). Support is very simple, SPL after finishes DDR training returns back to the BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and executes U-Boot proper. To generate correct kwbimage NAND header, it is required to set following Kconfig options: CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION They are used only by make / mkimage when generating final kwbimage. CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig option which is set into kwbimage NAND_BADBLK_LOCATION header field. Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: spl: Fix support for loading U-Boot proper from SD cardPali Rohár
Marvell BootROM loads MMC image from sector 0 (HW boot or data partition) and SD image from sector 1. So for SD card booting it is needed to not use constant CONFIG MMC options and instead of them it is needed to define functions spl_mmc_boot_mode() spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime based on MMC or SD card. Calculation of SD card sector expects following values: CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: spl: Load proper U-Boot from selected eMMC boot partitionPali Rohár
When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL) from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC boot partition. Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: spl: Remove checks for BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2Pali Rohár
BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all Armada SoCs have only one mmc controller. So remove references to non-existent second mmc controller. Fixes: f830703f4284 ("arm: mvebu: Check that kwbimage blockid matches boot mode") Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: spl: Fix parsing SATA kwbimagePali Rohár
Despite the official specification, Marvell BootROM does not interpret srcaddr from SATA image as number of sectors the beginning of the hard drive, but as number of sectors relative to the main header. To process SATA kwbimage and load U-Boot proper from it in the same way as Marvell BootROM, it is needed to interpret srcaddr as relative offset to the main header. This change fixes booting of U-Boot proper from SPL code in SATA image. Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <[email protected]>
2023-03-01arm: mvebu: spl: Fix parsing SDIO kwbimagePali Rohár
Despite the official specification, Marvell BootROM does not interpret srcaddr from SDIO image as offset in number of sectors (like for SATA image), but as offset in bytes (like for all other images except SATA). To process SDIO kwbimage and load U-Boot proper from it in the same way as Marvell BootROM, it is needed to interpret srcaddr in bytes. This change fixes booting of U-Boot proper from SPL code stored in SDIO image. Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <[email protected]>
2023-02-28board: rockchip: add Radxa ROCK5B Rk3588 boardEugen Hristev
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa. There are tree variants depending on the DRAM size : 4G, 8G and 16G. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 4/8/16GB memory LPDDR4x Mali G610MC4 GPU MIPI CSI 2 multiple lanes connector eMMC module connector uSD slot (up to 128GB) 2x USB 2.0, 2x USB 3.0 2x HDMI output, 1x HDMI input Ethernet port 40-pin IO header including UART, SPI, I2C and 5V DC power in USB PD over USB Type-C Size: 85mm x 54mm Kernel commits: a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board") 6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b") Signed-off-by: Eugen Hristev <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: rk3588: Read cpuid from otpJonas Karlman
Read cpuid from otp and set ethaddr for RK3588. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: rk3568: Read cpuid from otpJonas Karlman
The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs. Add and use a CFG_CPUID_OFFSET to define this offset. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: misc: Set eth1addr mac addressJonas Karlman
Set eth1addr in addition to ethaddr. Also allow fdt fixup of ethernet mac addresses when CMD_NET is disabled. Set ethaddr and eth1addr based on HASH and SHA256 options. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28board: rockchip: Add Edgeble Neural Compute Module 6Jagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. General features: - Rockchip RK3588 - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neural Compute Module 6(Neu6) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. Neu6 needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6(Neu6) IO platform. Boot log for the record, DDR Version V1.08 20220617 LPDDR4X, 2112MHz channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB Manufacturer ID:0x6 CH0 RX Vref:31.7%, TX Vref:21.8%,21.8% CH1 RX Vref:30.7%, TX Vref:22.8%,23.8% CH2 RX Vref:30.7%, TX Vref:22.8%,22.8% CH3 RX Vref:30.7%, TX Vref:21.8%,21.8% change to F1: 528MHz change to F2: 1068MHz change to F3: 1560MHz change to F0: 2112MHz out U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Trying to boot from MMC1 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang NOTICE: BL31: Built : 14:15:50, Jul 18 2022 INFO: ext 32k is not valid INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: system boots from cpu-hwid-0 INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001 INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz INFO: BL31: Initialising Exception Handling Framework INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9 U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530) Model: Edgeble Neu6A IO Board DRAM: 7.5 GiB (effective 3.7 GiB) Core: 71 devices, 15 uclasses, devicetree: separate MMC: mmc@fe2c0000: 0 Loading Environment from nowhere... OK In: serial@feb50000 Out: serial@feb50000 Err: serial@feb50000 Model: Edgeble Neu6A IO Board Net: No ethernet found. Hit any key to stop autoboot: 0 => Add support for Edgeble Neu6 Model A IO Board. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc nodeJagan Teki
Booting from SDMMC is one of the fast and easy booting methods for initial support of any SoC to upstream more features.  This patch is trying to add the sdmmc node for rk3588 and added as u-boot specific node in -u-boot.dtsi as upstream Linux is not supporting yet. As soon as Linux supports it, a sync of the Linux device tree would eventually drop this node.  Clock properties as added according to the rockchip mmc driver but the actual definition might add scmi clocks into 0 and 1 indexes. This is due to scmi clock are not supporting in upstream U-Boot. Properly addition of scmi clock would eventually follow sdmmc clock definition of Linux once they upstreamed. Signed-off-by: Jagan Teki <[email protected]>
2023-02-28ARM: dts: rockchip: Add rk3588-u-boot.dtsiJagan Teki
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties for Rockchip RK3588 SoC to boot the SPL. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm: rockchip: Add RK3588 arch core supportJagan Teki
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM. Add arch core support for it. Signed-off-by: Jagan Teki <[email protected]> Signed-off-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IOJagan Teki
Neural Compute Module 6(Neu6) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. Neu6 needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6(Neu6) IO platform. commit <a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO") Add support for Edgeble Neu6 Model A IO Board. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoMJagan Teki
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. General features: - Rockchip RK3588 - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neu6 needs to mount on top of associated Edgeble IO boards for creating complete platform solutions. Enable eMMC for now to boot Linux successfully. commit <3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM") Add support for Edgeble Neu6 Model A SoM. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: Add base DT for rk3588 SoCJagan Teki
This initial version supports CPU, dma, interrupts, timers, UART and SDHCI (everything necessary to boot Linux on this system on chip) as well as Ethernet, I2C, PWM and SPI. The DT is split into rk3588 and rk3588s, which is a reduced version (i.e. with less peripherals) of the former. commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588 SoC") commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data") Signed-off-by: Jianqun Xu <[email protected]> Signed-off-by: Kever Yang <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm: rockchip: Add ioc header for rk3588Jagan Teki
Add IOC unit header include for rk3588. Signed-off-by: Steven Liu <[email protected]> Signed-off-by: Joseph Chen <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm: rockchip: Add grf header for rk3588Jagan Teki
Add GRF header for Rockchip RK3588. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm: rockchip: Add cru header for rk3588Jagan Teki
Add clock and reset unit header include for rk3588. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: add gpio-ranges property to gpio nodesChris Morgan
Add gpio-ranges property to GPIO nodes so that the bank ID can be correctly derived for each GPIO bank. Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: rk3568: enable automatic power savingsChris Morgan
It enables automatic clock gating on idle, disables the eDP phy by default, and sets the core pvtpll ring length. It is reported this lowers the temperature on at least one SoC by 7C. Signed-off-by: Peter Geis <[email protected]> Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: rk3568: add boot device detectionChris Morgan
Enable spl to detect which device it was booted from. Signed-off-by: Peter Geis <[email protected]> Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: Sync rk356x from Linux mainChris Morgan
Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of this writing). Note that this will rename the rk3568-evb to rk3568-evb1-v10. Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28dts: rockchip: px30: add gpio-ranges property to gpio nodesChris Morgan
Add the gpio-ranges property to each GPIO node for use in deriving the correct bank ID. Note that invoking "gpio status -a" no longer causes the board to hit a "Synchronous Abort". Fixes: 537b1a277479 ("rockchip: add px30 devicetrees") Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: rk3568: Select DM_REGULATOR_FIXEDManoj Sai
Select the DM_REGULATOR_FIXED on RK3568 platform. Co-developed-by: Suniel Mahesh <[email protected]> Signed-off-by: Suniel Mahesh <[email protected]> Signed-off-by: Manoj Sai <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/ratesJagan Teki
combphy1 is failing to probe due to unhandled assigned-clocks and assigned-clocks-rates. => usb start starting USB... Bus usb@fd000000: Failed to get PHY1 for usb@fd000000 Port not available. Bus usb@fd800000: USB EHCI 1.00 There is no real requirement for them in U-Boot to handle, hence mark them as deleted-properties for the probe to success Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28board: rockchip: Add Radxa Compute Module 3 IO BoardJagan Teki
Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi Reviewed-by: Kever Yang <[email protected]> Signed-off-by: Jagan Teki <[email protected]>
2023-02-28arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IOJagan Teki
Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Specification: - 1x HDMI, - 2x MIPI DSI - 2x MIPI CSI2 - 1x eDP - 1x PCIe card - 2x SATA - 2x USB 2.0 Host - 1x USB 3.0 - 1x USB 2.0 OTG - Phone jack - microSD slot - 40-pin GPIO expansion header - 12V DC Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3 IO Board. Co-developed-by: FUKAUMI Naoki <[email protected]> Signed-off-by: FUKAUMI Naoki <[email protected]> Co-developed-by: Manoj Sai <[email protected]> Signed-off-by: Manoj Sai <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3Jagan Teki
Radxa Compute Module 3(CM3) is one of the modules from a series System On Module based on the Radxa ROCK 3 series and is compatible with Raspberry Pi CM4 pinout and form factor. Specification: - Rockchip RK3566 - up to 8GB LPDDR4 - up to 128GB high performance eMMC - Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless, BT 5.0, BLE with onboard and external antenna. - Gigabit Ethernet PHY Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3. Reviewed-by: Kever Yang <[email protected]> Co-developed-by: FUKAUMI Naoki <[email protected]> Signed-off-by: FUKAUMI Naoki <[email protected]> Signed-off-by: Jagan Teki <[email protected]>
2023-02-28rockchip: rk3568: Move DM_RESET in arch kconfigJagan Teki
Like other rockchip SoCs, DM_RESET is useful across rk3568 platform. Select it from arch kconfig. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S supportAkash Gajjar
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from Linux 6.2.0-rc7. ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, - 256MB/512MB DDR3 RAM - SD, NAND flash (optional on board 1/2/4/8Gb) - 100MB ethernet, PoE (optional) - Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module - USB2.0 Type-A HOST x1 - USB3.0 Type-C OTG x1 - 26-pin expansion header - USB Type-C DC 5V Power Supply Linux commit commit for the same, <2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Akash Gajjar <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board supportAkash Gajjar
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7 Board Specifications - Rockchip RK3568 - 2/4/8GB LPDDR4 3200MT/s - eMMC socket, SD card slot - GbE LAN - PCIe 3.0/2.0 - M.2 Connector - 3.5mm Audio jack with mic - HDMI 2.0, MIPI DSI/CSI - USB 3.0 Host/OTG, USB 2.0 Host - 40-pin GPIO expansion ports - USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A Refer Linux commit <22a442e6586c> ("arm64: dts: rockchip: add basic dts for the radxa rock3 model a") Signed-off-by: Akash Gajjar <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: Use an external TPL binary on RK3568Jonas Karlman
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then jumps to U-Boot SPL to continue the normal boot flow. However, there is no support to initialize DRAM on RK35xx SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image. Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a bootable u-boot-rockchip.bin image for RK3568. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]> Tested-by: Eugen Hristev <[email protected]>
2023-02-28rockchip: dts: rk3328: fix sdram paramsJonas Karlman
The rk3328 sdram driver read sdram parameters from the devicetree into a struct rk3328_sdram_params using dev_read_u32_array. After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") changed the size of struct ddr_pctl_regs, a member of struct rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328. Add ten u32 to the sdram parameter array in devicetree to align with this size change. This fixes DRAM initialization on RK3328. Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Tested-by: Jagan Teki <[email protected]> # roc-rk3328-cc
2023-02-28rockchip: sdram: add dram bank with usable memory beyond 4GBJonas Karlman
Add a second dram bank of usable memory beyond the blob of space for peripheral near 4GB. Any memory that exists beyond the 4GB mark is added to the second bank. Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28rockchip: sdram: add basic support for sdram reg info version 3Jonas Karlman
Newer DRAM initialization blobs from vendor can encode sdram info in a new version 3 format. The new format makes use of more bits in sys_reg3 compared to the version 2 format. Add basic support for detecting the version 3 format and decoding the high bits used for ddrtype. This fixes decode of sdram size on my RK3568 boards that have LPDDR4X. Details on the new format was deciphered from vendor u-boot commit [1]. [1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfoChristian Kohlschütter
Provide human-readable manufacturer and product names for the FriendlyELEC NanoPi R4S. Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default. Signed-off-by: Christian Kohlschütter <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-02-28ARM: dts: at91: sama7g5: fix clock id for ebi nodeMihai Sain
The PMC_MCK1 clock id for the ebi node is 23. Fixes: 746b738224ad ("ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT") Reviewed-by: Eugen Hristev <[email protected]> Signed-off-by: Mihai Sain <[email protected]>
2023-02-28tpm: Separate out the TPM tests for v1 and v2Simon Glass
Currently there is only one test and it only works on TPM v2. Update it to work on v1.2 as well, using a new function to pick up the required TPM. Update sandbox to include both a v1.2 and v2 TPM so that this works. Split out the existing test into two pieces, one for init and one for the v2-only report_state feature. Acked-by: Ilias Apalodimas <[email protected] Signed-off-by: Simon Glass <[email protected]> Signed-off-by: Ilias Apalodimas <[email protected]>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini
Prepare v2023.04-rc3
2023-02-23Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegraTom Rini
2023-02-23ARM: tegra20: implement BCT patchingSvyatoslav Ryhel
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypt BCT. Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20 Signed-off-by: Ramin Khonsari <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Tom <[email protected]>
2023-02-23ARM: tegra30: implement BCT patchingRamin Khonsari
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypted BCT. Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30 Signed-off-by: Ramin Khonsari <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Tom <[email protected]>
2023-02-23ARM: tegra: crypto: extend crypto functionalSvyatoslav Ryhel
Add support for encryption, decryption and signinig with non-zero key saving backward compatibility. Signed-off-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Tom <[email protected]>
2023-02-23ARM: tegra: expose crypto module for all Tegra SoCsSvyatoslav Ryhel
Move crypto module from T20 only into common Tegra dir. Signed-off-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Tom <[email protected]>
2023-02-23board: tegra30: switch to updated pre-dm i2c writeSvyatoslav Ryhel
Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding <[email protected]> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <[email protected]> Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Tom <[email protected]>
2023-02-23ARM: tegra: create common pre-dm i2c writeSvyatoslav Ryhel
This implementation allows pwr i2c writing on early SPL stages when DM is not yet setup. Such writing is needed to configure main voltages of PMIC on early SPL for bootloader to boot properly. Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF T30 Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <[email protected]> # LG P895 T30 Tested-by: Thierry Reding <[email protected]> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <[email protected]> Signed-off-by: Tom <[email protected]>
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