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2022-09-16blk: Switch over to using uclass IDsSimon Glass
We currently have an if_type (interface type) and a uclass id. These are closely related and we don't need to have both. Drop the if_type values and use the uclass ones instead. Maintain the existing, subtle, one-way conversion between UCLASS_USB and UCLASS_MASS_STORAGE for now, and add a comment. Signed-off-by: Simon Glass <[email protected]>
2022-09-16sandbox: Avoid defining HAVE_BLOCK_DEVICE in KonfigSimon Glass
This is not needed as it is implied or selected by other options anyway. Signed-off-by: Simon Glass <[email protected]>
2022-09-16blk: Enable CONFIG_BLK for all mediaSimon Glass
Enable this option on all boards which support block devices. Drop the related depencies on BLK since these are not needed anymore. Disable BLOCK_CACHE on M5253DEMO as this causes a build error. Signed-off-by: Simon Glass <[email protected]>
2022-09-15brppt1: Cleanup device treeBernhard Messerklinger
* Remove unnecessary device tree nodes which are not needed in U-Boot directly. * Move all U-Boot specific device tree properties to u-boot dtsi. Signed-off-by: Bernhard Messerklinger <[email protected]> Reviewed-by: Wolfgang Wallner <[email protected]>
2022-09-15brppt1: Fix SPL boot stageBernhard Messerklinger
Commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs the am335x device tree with the latest linux kernel am335x device tree. That causes problems with device tree in SPL stage. To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the synced bus addresses correctly. A custom U-Boot device tree is also needed since the SPL build removes bus properties from bus nodes which are not explicitly marked with the u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of the in the SPL needed devices must be marked with u-boot,dm-pre-reloc. Also since there is no driver for "ti,sysc" compatible property in SPL the buses marked with this compatible string must also be marked with compatible = "simple-bus" to make the underlying devices visible in SPL. Otherwise the matching device drivers aren't found and the uclass drivers are dropped. Signed-off-by: Bernhard Messerklinger <[email protected]> Reviewed-by: Wolfgang Wallner <[email protected]>
2022-09-15brppt1: Remove unused board variantsBernhard Messerklinger
The SPI and NAND board variants never went into production. Drop those board variants. Signed-off-by: Bernhard Messerklinger <[email protected]> Reviewed-by: Wolfgang Wallner <[email protected]>
2022-09-14dm: core: Add functions to read 8/16-bit integersStefan Herbrechtsmeier
Add functions to read 8/16-bit integers like the existing functions for 32/64-bit to simplify read of 8/16-bit integers from device tree properties. Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-09-14Add in the ability to load and boot an uncompressed kernel image during the ↵Nathan Barrett-Morrison
Falcon Mode boot sequence. This is required for architectures which do not support compressed kernel images (i.e. ARM64). This is only used while not booting via FIT image. Signed-off-by: Nathan Barrett-Morrison <[email protected]> Cc: Tom Rini <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2022-09-13arm: dts: aspeed: Update SPI flash node settingsChin-Ting Kuo
For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <[email protected]>
2022-09-13xilinx: Fix mdio bus description for vck190-scMichal Simek
Current behavior is that eth_phy_get_mdio_bus Net: FEC: can't find phy-handle ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5b7da5808136b3f579c0cf7a3431b56c758655e9.1662460749.git.michal.simek@amd.com
2022-09-13ARM: zynq: DT: List OCM memoryMichal Simek
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/a951dbe885640197efe3e91bb9fa5caedb54b387.1662460712.git.michal.simek@amd.com
2022-09-13ARM: zynq: Align qspi node name with Linux kernelMichal Simek
Nodes should follow generic rules where compatible and reg properties should be listed on the top of node. That's why sync it up. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/922dca6227cb0aa4f79e6d3595c5f280ba020684.1662460540.git.michal.simek@amd.com
2022-09-13arm64: versal: Define zynqmp_mmio_write() for versalMichal Simek
GQSPI driver is using it but this function is never called for Versal because it is removed by linker. But function should be declared to avoid this build warning: drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay': drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function 'zynqmp_mmio_write' [-Wimplicit-function-declaration] 378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-09-13microblaze: add arch_print_bdinfo() implementationOvidiu Panait
Allow bdinfo command to print icache/dcache information: U-Boot-mONStR> bdinfo boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x04000000 -> size = 0x04000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 9600 bps relocaddr = 0x07f76000 reloc off = 0x02f76000 Build = 32-bit current eth = unknown ethaddr = (not set) IP addr = <NULL> fdt_blob = 0x07fec7e0 new_fdt = 0x00000000 fdt_size = 0x00000000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0 reserved.cnt = 0x1 reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0 devicetree = embed icache = 32 KiB icache line = 4 Bytes dcache = 32 KiB dcache line = 4 Bytes Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-09-13ARM: zynq: Align bss and end of u-boot image to 64bitsMichal Simek
The main reason is that DT memory reserved code is expecting DT to be 64bit aligned. For more information take a look at commit 5bd5ee02b23b ("xilinx: zynqmp: Check that DT is 64bit aligned"). Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: add ref_clk property for REFCLKPER calculationPiyush Mehta
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ calculation. This property configure correct value for SOF/ITP counter and period of ref_clk. This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores. Signed-off-by: Piyush Mehta <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: Add missing tca6416 to zynqmp SCMichal Simek
Add missing tca6416 i2c gpio controller to SC dts file. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
2022-09-13arm: dts: Add xlnx prefix to GEM compatible stringHarini Katakam
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx prefix. Add this new compatible string and retain the existing string for compatibility with uboot drivers. Signed-off-by: Harini Katakam <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
2022-09-13arm64: zynqmp: Add mtd partition for secure OS storage areaAmit Kumar Mahapatra
Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage" Signed-off-by: Amit Kumar Mahapatra <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
2022-09-13arm: mvebu: Fix moving internal registersPali Rohár
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") moved code from file cpu.c to lowlevel.c, which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE. But the steps describing how to do it correctly were documented only in older U-Boot versions and commit cefd764222ee ("arm: mvebu: Fix internal register config on A38x") probably unintentionally removed important details about MMU from code comments around. Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") implemented code movement according to (now incomplete) comments which resulted in semi-broken code. The result is that I-cache is currently disabled for all Armada 38x boards and maybe there are some other (unreported / undetected) issues. Reimplement it correctly. First flush all caches, then disable MMU and L2 cache and then move Marvell internal registers. There is no need to explicitly disable I-cache. After this change lzmadec command with lzma image of 0x7000000 bytes is doing decompression just 5 seconds. Before this change it was 30 seconds. To make lowlevel.S code more readable, extend asm/pl310.h header file to be compatible with assembler and use macros from this file. Fixes: 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-13arm: mvebu: Enable L2 cache also on Armada 38xPali Rohár
For some unknown reason when L2 cache is disabled on Armada 385 then loadb, loadx and loady commands do not work with higher baudrates than 115200 (they just abort transfer) and lzmadec command with lzma image of size 0x7000000 (maybe even smaller, we tested this one) is doing decompression for more than 2 minutes. After enabling L2 cache decompression takes only 30s and loadb, loadx and loady are stable and working fine. git bisect identified problematic commit 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit above issues were not present. But investigation showed that above issue was possible to reproduce also by reverting that commit and forcing compiler to do inline optimization of mvebu_soc_family() function. Which seems that the root of this issue is in caches and position of instruction of segments. So currently it is unknown what is or was broken, but code movement, code inlining or other compiler optimization triggered it. Commit 3e5ce7ceeb94 ("arm: mvebu: Enable L2 cache on Armada XP") mentioned that enabling L2 cache on Armada XP improved performance and that Armada 38x has L2 disabled (which is default state) and if needed it has to be enabled in separate patch. As enabling L2 cache also improve performance on Armada 38x, enable it. Note that Aurora cache in no outer mode is available only on Armada XP, hence it is not touched for Armada 38x code. Fixes: 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") Reported-by: Marek Behún <[email protected]> Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-13arm: mvebu: lowlevel.S: Use CR_M from asm/system.hPali Rohár
Replace magic constant 1 when disabling MMU by macro CR_M from include header file asm/system.h. Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-13arm: mvebu: Guard non-AXP code by checking for AXPPali Rohár
Commit c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") introduced branch for non-AXP code which was guarded by A38X condition. Fix this issue by checking for AXP platform, not by A38X. Fixes: c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-13arm: mvebu: Fix function enable_cachesPali Rohár
Commit 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") broke support for caches on all Armada SoCs. Before that commit there was code: if (mvebu_soc_family() != MVEBU_SOC_A375) { dcache_enable(); } And after that commit there is code: if (IS_ENABLED(CONFIG_ARMADA_375)) { dcache_enable(); } Comment above this code says that d-cache should be disabled on Armada 375. But new code inverted logic and broke Armada 375 and slowed down all other Armada SoCs (including A38x). Fix this issue by changing logic to: if (!IS_ENABLED(CONFIG_ARMADA_375)) { dcache_enable(); } Which matches behavior prior that commit. Fixes: 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-13arm: mvebu: Mark constant data with const keywordPali Rohár
Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2022-09-12zynq: Convert arm twd timer to DM driverStefan Herbrechtsmeier
Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-09-08Merge tag 'u-boot-stm32-20220907' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - simplify the STM32MP15x package parsing code - remove test on CONFIG_DM_REGULATOR in stm32mp1 board and enable CONFIG_DM_REGULATOR for stm32f769-disco - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start' after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>) - Fix SYS_HZ_CLOCK value for stih410-b2260 board - Switch STMM32MP15x DHSOM to FMC2 EBI driver - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
2022-09-07ARMv8/sec_firmware: Convert to use fit_get_data_conf_propSean Anderson
This reduces sec_firmware_get_data to a single call to fit_get_data_conf_prop. I think sec_firmware_check_copy_loadable could also be converted, but it does not map as straightforwardly, so I have left it for a future cleanup. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-09-07ARMv8/sec_firmware: Remove SEC_FIRMWARE_FIT_CNF_NAMESean Anderson
The config to use for FIT images can be better specified by enabling CONFIG_MULTI_DTB_FIT and implementing board_fit_config_name_match. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-09-06ARM: dts: stm32mp15: remove hwlocks from pinctrlEtienne Carriere
Removes hwlocks properties from stm32mp151 pinctrl node. These locks could be used for other purpose, depending on board and software configuration hence do not enforce their use to protect pinctrl devices. This patch is an alignment with Linux device tree with v6.0 as the hwsem support wasn’t yet added in pincontrol in kernel. It avoids issues when the Linux kernel is started with the U-Boot device tree. Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Signed-off-by: Etienne Carriere <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2022-09-06ARM: stm32: Switch DHSOM to FMC2 EBI driverMarek Vasut
Perform long overdue conversion of ad-hoc FMC2 EBI bus initialization to upstream FMC2 EBI driver. No functional change. Signed-off-by: Marek Vasut <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2022-09-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2022-09-06Merge tag 'fsl-qoriq-2022-9-6' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq Reset fixes for p1_p2_rdb_pc Fix use after free issue fix in fsl_enetc.c Fix for fsl ddr: make bank_addr_bits reflect actual bits sl28 board update
2022-09-06ARM: dts: stm32: Fix display-timings settings for stm32f746-discoPatrice Chotard
Since commit ef4ce6df3289 "video: stm32: stm32_ltdc: fix data enable polarity" The panel display output wasn't functional anymore. Device tree display-timings de-active property value must be updated to 1. Signed-off-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2022-09-06stm32mp: simplify the STM32MP15x package parsing codePatrick Delaunay
Simplify the package parsing code for STM32MP15X as package can be affected with get_cpu_package() result. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2022-09-06board: freescale: p1_p2_rdb_pc: Turn off watchdog before resetPali Rohár
P1/P2 RDB boards have external max6370 watchdog connected to CPLD and this watchdog is not deactivated on board reset. So if it is active during board reset, it can trigger another reset when CPU is booting U-Boot. To prevent possible infinite reset loop caused by external watchdog, turn it off before reset. Do it via a new board_reset_prepare() callback which is called from do_reset() function before any reset sequence. Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-09-06board: freescale: p1_p2_rdb_pc: Avoid usage of CPLD's system reset registerPali Rohár
CPLD's system reset register is buggy and requires workaround in U-Boot. So use this kind of board reset only when there is no other reset option. Introduce a new board_reset_last() callback which is last-stage board-specific reset and implement CPLD's system reset in this new board_reset_last() callback instead of board_reset() callback. Fixes: 20fb58fc5a1c ("board: freescale: p1_p2_rdb_pc: Implement board_reset()") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-09-06riscv: dts: sifive: Synchronize FU740 and Unmatched DTIcenowy Zheng
These DT files are synchronized from Linux 5.19. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2022-09-06dt-bindings: clock: sifive: sync FU740 PRCI clock binding headerIcenowy Zheng
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2022-09-06armv8: layerscape: spl: mark OCRAM as non-secureMichael Walle
By default the OCRAM is marked as secure. While the SPL runs in EL3 and thus can access it, DMA devices cannot. Mark the whole OCRAM as non-secure. This will fix MMC and SD card boot on LS1028A when using SPL instead of TF-A. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2022-09-05riscv: dts: Sync important Unmatched pmic and qspi0 changes from LinuxJessica Clarke
This adds the onkey, RTC and watchdog children to the DA9063 PMIC node, fixes the compatible for qspi0's flash node to match the official DT schema (it being an is25wp256 is discoverable, hence jedec,spi-nor is the only compatible that should be present) and exposes the card detect GPIO. Note that the device trees still diverge in some places (including important things like the PCIe controller's clock name) and should be cleaned up so that a common device tree is used in both projects rather than having different bindings. This patch does not attempt to do that, merely expose important functionality present in Linux's that is not in U-Boot's so that it can be used without the OS providing its own bundled copy. Signed-off-by: Jessica Clarke <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
2022-09-04Merge tag 'u-boot-rockchip-20220905' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - migrate to use binman for U-Boot image generate on rockchip platform; - Some fixes for rk3399 and rk3308;
2022-09-04rockchip: add u-boot-rockchip-spi.bin image for booting from SPI-NOR flashQuentin Schulz
This new image is similar to u-boot-rockchip.bin except that it's destined to be flashed on SPI-NOR flashes. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-09-04rockchip: allow to build SPI images even without HAS_ROM optionQuentin Schulz
This prepares for the creation of a u-boot-rockchip-spi.bin image similar to u-boot-rockchip.bin to the exception it's destined for SPI-NOR flashes instead of MMC storage medium. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04rockchip: generate u-boot-rockchip.bin with binman for ARM64 boardsQuentin Schulz
This allows to build u-boot-rockchip.bin binary with binman for Rockchip ARM64 boards instead of the legacy Makefile way. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-09-04rockchip: generate idbloader.img content for u-boot-rockchip.bin with binman ↵Quentin Schulz
for ARM idbloader.img content - currently created by way of Makefile - can be created by binman directly. So let's do that for Rockchip ARM platforms. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04rockchip: rk3399: sync spl_boot_devices_tbl and boot_devices node pathsQuentin Schulz
While technically not a bug, let's have some consistency in paths returned by u-boot,spl-boot-order look-up and the one saved in u-boot,spl-boot-device by syncing spl_boot_devices_tbl and boot_devices node paths. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Tested-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04rockchip: rk3399: fix incorrect boot-device in u-boot, spl-boot-deviceQuentin Schulz
On RK3399, mmc0 is eMMC and mmc1 is SD card, c.f. console: MMC: mmc@fe320000: 1, mmc@fe330000: 0 In arch/arm/mach-rockchip/spl-boot-order.c:board_boot_order, the boot_device (BOOT_DEVICE_*) value is gotten from spl_node_to_boot_device function. Said function returns BOOT_DEVICE_MMC1 for mmc0 (eMMC) and BOOT_DEVICE_MMC2 for mmc1 (SD card). Since the SD card controller is at mmc@fe320000, it should be associated with BOOT_DEVICE_MMC2 and not BOOT_DEVICE_MMC1. Same applies to eMMC. Let's fix that by swapping the two BOOT_DEVICEs. Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Tested-by: Xavier Drudis Ferran <[email protected]>
2022-09-04rockchip: rk3308: fix same-as-spl boot orderJohn Keeping
Rockchip SoCs need the boot_devices array defined in order to map the bootloader's value to a U-Boot device. Implement this for rk3308. Signed-off-by: John Keeping <[email protected]> Reviewed-by: Philipp Tomsich <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2022-09-04rockchip: rk3399: boot_devices: fix eMMC node nameQuentin Schulz
When idbloader.img is flashed on the eMMC, the SPL still tries to load from SPI-NOR first. This is due to an incorrect look-up in the Device Tree. Since commit 822556a93459 ("arm: dts: sync the Rockhip 3399 SoCs from Linux"), the node name (but not label) changed from sdhci@fe330000 to mmc@fe330000 meaning U-Boot SPL is not looking for the correct node name anymore and fails to find the "same-as-spl" node when eMMC is the medium from which the SPL booted. Fixes: 822556a93459 ("arm: dts: sync the Rockhip 3399 SoCs from Linux") Cc: Quentin Schulz <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Xavier Drudis Ferran <[email protected]> Reviewed-by: Artem Lapkin <[email protected]> Tested-by: Artem Lapkin <[email protected]> Tested-by: Lapkin Artem <[email protected]> Tested-by: Lapkin Artem <[email protected]> Reviewed-by: Kever Yang <[email protected]>
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