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Add a fuzzing engine driver for the sandbox to take inputs from
libfuzzer and expose them to the fuzz tests.
Signed-off-by: Andrew Scull <[email protected]>
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Add an implementation of LLVMFuzzerTestOneInput() that starts the
sandbox on a secondary thread and exposes a function to synchronize the
generation of fuzzing inputs with their consumption by the sandbox.
Signed-off-by: Andrew Scull <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Move the program's entry point to os.c, in preparation for a separate
fuzzing entry point to be added.
Signed-off-by: Andrew Scull <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add CONFIG_ASAN to build with the Address Sanitizer. This only works
with the sandbox so the config is likewise dependent. The resulting
executable will have ASAN instrumentation, including the leak detector
that can be disabled with the ASAN_OPTIONS environment variable:
ASAN_OPTIONS=detect_leaks=0 ./u-boot
Since u-boot uses its own dlmalloc, dynamic allocations aren't
automatically instrumented, but stack variables and globals are.
Instrumentation could be added to dlmalloc to poison and unpoison memory
as it is allocated and deallocated, and to introduce redzones between
allocations. Alternatively, the sandbox may be able to play games with
the system allocator and somehow still keep the required memory
abstraction. No effort to address dynamic allocation is made by this
patch.
The config is not yet enabled for any targets by default.
Signed-off-by: Andrew Scull <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.
Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.
Signed-off-by: Andrew Scull <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Rename the sections used for defining sandbox command line options so
that they don't start with a '.'. ELF says that sections starting with a
'.' are reserved for system use, but the sandbox runs as a normal user
process so should be using user sections instead.
Clang's ASAN adds redzones to non-user sections and the extra padding
meant that the list of options was being corrupted. Naming the sections
as user sections avoids this issue as clang handles them as we intended.
Signed-off-by: Andrew Scull <[email protected]>
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Rename the sections used for placing the EFI runtime so that they don't
start with a '.'. ELF says that sections starting with a '.' are
reserved for system use, but the sandbox runs as a normal user process
so should be using user sections instead.
Clang's ASAN adds redzones to non-user sections and the extra padding
meant that the list of options was being corrupted. Naming the sections
as user sections avoids this issue as clang handles them as we intended.
Signed-off-by: Andrew Scull <[email protected]>
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This was previously needed, but U-Boot is now capable of parsing
the new "phy-connection-type" property that is already used in
the main devicetree.
Signed-off-by: Frieder Schrempf <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
This also fixes the currently broken ethernet support:
Before:
Net: Could not get PHY for FEC0: addr 0
After:
Net: eth0: ethernet@30be0000
Signed-off-by: Frieder Schrempf <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Timeouts are not expected to happen and are handled as fatal errors.
Increase all timeouts to 1 second as defensive measure to avoid relying
on the timing behaviour of certain firmware versions or configurations.
Signed-off-by: Janne Grunau <[email protected]>
Reviewed-by: Mark Kettenis <[email protected]>
Tested-by: Mark Kettenis <[email protected]>
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The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
current minimal RTKit implementation. It does not provide buffers for
the firmware's buffer requests. The ANS2 firmware included in macOS 11
and 12 tolerates this. The firmware included in the first macOS 13 beta
requires buffers for the crashlog and ioreport endpoints to function.
In the case of the NVMe the buffers are physical memory. Access to
physical memory is guarded by what Apple calls SART.
Import m1n1's SART driver (exclusively used for the NVMe controller).
Implement buffer management helpers for RTKit. These are generic since
other devices (none in u-boot so far) require different handling.
Signed-off-by: Janne Grunau <[email protected]>
Reviewed-by: Mark Kettenis <[email protected]>
Tested-by: Mark Kettenis <[email protected]>
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Add Nuvoton BMC npcm750 otp driver
Signed-off-by: Jim Liu <[email protected]>
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add nuvoton BMC npcm750 AES driver
Signed-off-by: Jim Liu <[email protected]>
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AST2600 supports boot from SPI(mmap), eMMC, and UART.
This patch adds the boot mode detection and return the
corresponding boot device type.
Signed-off-by: Chia-Wei Wang <[email protected]>
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The commit b583348ca8c8 ("image: fit: Align hash output buffers") places
the hash output buffer at the .bss section. However, AST2600 by default
executes SPL in the NOR flash XIP way. This results in the hash output
cannot be written to the buffer as it is located at the R/X only region.
We need to move the .bss section out of the SPL body to the DRAM space,
where hash output can be written to. This patch includes:
- Define the .bss section base and size
- A new SPL linker script is added with a separate .bss region specified
- Enable CONFIG_SPL_SEPARATE_BSS kconfig option
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Neal Liu <[email protected]>
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The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.
The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.
Signed-off-by: Nick Hawkins <[email protected]>
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The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.
Info about SoC:
HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.
Signed-off-by: Nick Hawkins <[email protected]>
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Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
FPGA MPS3 board implementation of this platform. [2]
0: https://developer.arm.com/documentation/102360/0000
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://developer.arm.com/documentation/dai0550/c/
Signed-off-by: Rui Miguel Silva <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add the missing ethernet node in u-boot dts.
Signed-off-by: Anthoine Bourgeois <[email protected]>
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Seems that u-boot can't probe i2c bus at 2.6Mhz speed, so lower
the speed to the default value 100Khz.
v2: fix i2c1 frequency in the root omap3-u-boot.dtsi include.
Signed-off-by: Anthoine Bourgeois <[email protected]>
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This commit adds OMAP3 BeagleBoard devicetree files from Linux
v5.16.0.
This commit fixes CONFIG_DM_MMC warning.
v3: patch clean-up
Signed-off-by: Anthoine Bourgeois <[email protected]>
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Merge in v2022.07-rc5.
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https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
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A board might need to get the source of the RCW word, which is also the
boot source in most cases.
These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.
Signed-off-by: Michael Walle <[email protected]>
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Old size is stored in size variable and new size is in bootm_size variable.
Signed-off-by: Pali Rohár <[email protected]>
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Copy definition of PMC node from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <[email protected]>
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This reduce usage of per-board custom settings.
Signed-off-by: Pali Rohár <[email protected]>
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Effective page number mask for MAS2 register is stored in macro MAS2_EPN.
Fixes: 2146cf56821c ("Reworked FSL Book-E TLB macros to be more readable")
Signed-off-by: Pali Rohár <[email protected]>
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Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).
Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
are slightly complicated, but are really correct for P2020 platform.
Signed-off-by: Pali Rohár <[email protected]>
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When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to
conflicting functions like watchdog_reset(). So disable compilation of
mpc85xx watchdog_reset() function when CONFIG_WDT is enabled.
Signed-off-by: Pali Rohár <[email protected]>
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Copy definition of these nodes from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <[email protected]>
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Copy definition of DMA nodes from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <[email protected]>
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Copy definition of crypto node from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <[email protected]>
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Copy definition of MPIC nodes from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <[email protected]>
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These frequency calculations depend on the RCW format, which is not
dependent on any particular board. Switch to using ARCH symbols instead
of TARGET.
This whole function could probably use less ifdefs, but for now just do
a minimal conversion.
Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support")
Signed-off-by: Sean Anderson <[email protected]>
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This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.
Signed-off-by: Sean Anderson <[email protected]>
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QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).
This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").
Signed-off-by: Sean Anderson <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
- Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board
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https://github.com/tienfong/uboot_mainline
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Replace reference to the correct name STMicroelectronics
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.
To be functional this patch requires a modification in the debugger
,openocd for example, to update the STM32MP15 backup register when it is
required to debug SPL after reset. After deeper analysis this behavior
will be never supported in tools so the associated code, will be never
used and the associated code can be removed.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0
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Introduce STM32MP15 function and defines to prepare the
STM32MP13 introduction.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Change-Id: I909b205e73dcf207e0216aae5905c3c52472020e
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Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan <[email protected]>
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan <[email protected]>
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.
Signed-off-by: Chee Hong Ang <[email protected]>
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add config CONFIG_STM32MP15_PWR to handle the
access to regulators managed by the PWR driver defined in
pwr_regulator.c
This driver is only used in U-Boot by STM32MP15x family.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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