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This partly fix commit 726404a66c773 ("airoha: rework RAM size handling
to support multiple RAM size")
The function get_effective_memsize() do not see non-global defines
of CFG_MAX_MEM_MAPPED, so the effective memory size will not be changed.
Fix the issue by putting definition of CFG_MAX_MEM_MAPPED to the proper
place.
Fixes: 726404a66c773 ("airoha: rework RAM size handling to support multiple RAM size")
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Enable CONFIG_OF_UPSTREAM to receive automatic
device tree updates for the Verdin AM62P.
Remove the now-obsolete device tree files:
- k3-am62p-verdin.dtsi
- k3-am62p-verdin-dev.dtsi
- k3-am62p-verdin-wifi.dtsi
- k3-am62p5-verdin-wifi-dev.dts
Signed-off-by: Ernest Van Hoecke <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2
zynqmp:
- DT updates
- Enable new commands
mbv:
- Simplify defconfigs
clk:
- Separate legacy handler and use SMC handler
misc:
- Tighten TTC Kconfig dependency
net:
- Add 10GBE support to Gem
pwm:
- cadence-ttc: Fix array sizes
fwu:
- Add platform hook support
spi:
- Remove undocumented cdns,is-dma property
video:
- Fix DPSUB RGB handling
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https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=398&view=results
- sata_mv / octeontx_hsmmc: Smatch fixes / patches (Andrew)
- dts: pxa1908: convert to OF_UPSTREAM (Duje)
- phy: marvell: Tighten MVEBU_COMPHY_SUPPORT dependencies (Tom)
- pci: mvebu: Unable to assign mbus windows for 2nd pcie controller (Tony)
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Remove cdns,is-dma DT property handling. Property is not the part of DT
binding and it is also hardcoded to value 1 in all DTs that's why remove it
because none is also testing value 0.
If there is any use case when this configuration should be supported this
patch can be reverted.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6205c6585589b423692b6ed063506b4c51c04c77.1760006086.git.michal.simek@amd.com
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Given how these options are used in the code, it doesn't make sense to
enable them for COMPILE_TEST. Make them depend on !COMPILE_TEST.
Signed-off-by: Tom Rini <[email protected]>
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Convert the PXA1908 platform and its coreprimevelte board to OF_UPSTREAM
and enable the few drivers found in the upstream DTS.
Signed-off-by: Duje Mihanović <[email protected]>
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When I migrated this to Kconfig in commit 68e54040ccc3 ("sandbox: Move
CONFIG_IO_TRACE to Kconfig") I didn't look hard enough for other
details. As explained in the README, this is valid for ARM too. So start
by making this be a prompted question and CMD_IOTRACE depend on IO_TRACE
being enabled. Next, migrate the information out of README and in to
the appropriate help text for existing options in Kconfig. Finally, make
this option be default y on SANDBOX but not selected as it's valid to
build without it.
Signed-off-by: Tom Rini <[email protected]>
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The way that the current readX/writeX macros are implemented on sandbox
means that when IO_TRACE is not enabled some code will throw up
incorrect warnings due to how sandbox_{read,write} is implemented. We
instead need to do the "uX __v; __v = sandbox..(..v); __v;" trick that
ARM does.
Signed-off-by: Tom Rini <[email protected]>
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We have had an implementation of the generic timer found in many v7m
chips since 2017, but as part of the Kconfig migration forgot to allow
it as it wasn't being used at the time. Allow it to be built.
Signed-off-by: Tom Rini <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27872
- Several improvements for kontron-sl-mx8mm.
- Add rauc to bootmeths to phycore_imx8mp.
- Fix imx93_frdm USB vendor ID.
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Enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the Toradex SMARC iMX8MP.
Remove the now obsolete device tree files:
- imx8mp-toradex-smarc-dev.dts
- imx8mp-toradex-smarc.dtsi
Signed-off-by: Ernest Van Hoecke <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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DTC is generating warnings about missing port like:
DTOVL arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
/fragment@5/__overlay__: graph port node name should be 'port'
...
That's why change description and add it directly to dpsub mode to contain
full description with also port.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/576630cc9696e21bef15bd1f0ca35e396adc4eca.1758529693.git.michal.simek@amd.com
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Some boards/designs with System Controller which are using SOMs need to
change PWM signal polarity that's why create label to be able to reference
them.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/7a392d79685e5b122528e8fe7617475c4f6fabab.1756803198.git.michal.simek@amd.com
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Upstream DP DT binding enforcing dp-connector and port description to
operate properly.
Co-developed-by: Rohit Visavalia <[email protected]>
Signed-off-by: Rohit Visavalia <[email protected]>
Co-developed-by: Nithish Kumar Naroju <[email protected]>
Signed-off-by: Nithish Kumar Naroju <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/15e863adca11431f68d37d732cd8a453e508ad91.1756803198.git.michal.simek@amd.com
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Describe every port by unique label for easier wiring with DT overlays.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/933151f48f236f64ec9e91b9da4f174460a269e6.1756803198.git.michal.simek@amd.com
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ti,tps546d24 is already described in DT binding and ti,tps546b24 should be
described in the same way that's why update compatible string to match
them.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/a247b2b57ebe52e9d23525bf4f96c4872288025d.1756803198.git.michal.simek@amd.com
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TF-A is using PSCI 1.0 version for quite a long time but it was never
reflected in DT.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/a3372ee9cce7fade7c9f707727e33d1cf569b607.1756803198.git.michal.simek@amd.com
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Fix comment inside comment by closing the first one properly.
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/779be02a8f0cfa1deab86dbfe8e575ab152d43f3.1756803198.git.michal.simek@amd.com
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On a few zcu106 boards USB devices (Dell MS116 USB Optical Mouse, Dell USB
Entry Keyboard) are not enumerated on linux boot due to commit
'b8745e7eb488 ("arm64: zynqmp: Fix usb node drive strength and slew
rate")'.
To fix it as a workaround revert to working version and then investigate
at board level why drive strength from 12mA to 4mA and slew from fast to
slow is not working.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/14d3408cf547ac188c07c10abb0ddfaac9d915c4.1756803198.git.michal.simek@amd.com
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Add i2c-mux-idle-disconnect property to an i2c mux node.
It is used to configure an i2c mux to disconnect all
its channels when idle.
Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/d75f31d72cadf6d98c0faa51239bf2b239797d2d.1756803198.git.michal.simek@amd.com
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Linux driver has been updated that only ti,tps53681 dt property is needed
and there is no need to provide second compatible string.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/609ee957931242ab6cde93e75eb3bd8afa769f12.1756803198.git.michal.simek@amd.com
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Default calibration is already in zynqmp.dtsi that's why make no sense to
describe it again.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6331bf84d7afaf8031d9cbb64354fcd8ca343d45.1756803198.git.michal.simek@amd.com
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Property was used long ago by internal Xilinx Linux driver but it is not
documented in DT binding that's why remove it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/546788df1a64c41e332463411ad99b1f3b40bc96.1756803198.git.michal.simek@amd.com
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When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.
Signed-off-by: Quanyang Wang <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/1ea8e5bdb9bfdcc1fc6670bf4b4e13c40fbdc00c.1756803198.git.michal.simek@amd.com
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Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.
The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.
Signed-off-by: Naman Trivedi <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Acked-by: Senthil Nathan Thangaraj <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
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In order for cmd/cache.c to link we need to add dummy icache functions
to mirror the dummy dcache functions as well as another dcache flush
function.
Signed-off-by: Tom Rini <[email protected]>
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Add initial support for AM62D2-EVM, Kconfig entries for binman, SPL,
base DTS files for u-boot and SPL, HS-SE and HS-FS support and initial
configs with SD-MMC, UART, eMMC and OSPI boot providing a baseline for
further enablement.
Also add labels and targets to AM62A-SK binman to enable AM62D2-EVM
builds to reuse existing binman infrastructure.
Technical Reference Manual - https://www.ti.com/lit/pdf/sprujd4
Schematics Link - https://www.ti.com/lit/zip/sprcal5
Signed-off-by: Paresh Bhagat <[email protected]>
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Linux kernel .get_temp() callback reports values in millicelsius,
U-Boot currently reports them in celsius. Align the two and report
in millicelsius. Update drivers accordingly. Update callsites that
use thermal_get_temp() as well.
The 'temperature' command now reports temperature in millicelsius
as well, with additional accuracy. This changes command line ABI
slightly.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: David Zang <[email protected]>
[trini: Update test/cmd/temperature.c]
Signed-off-by: Tom Rini <[email protected]>
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As of commit f98d812e5353 ("power: regulator: Add vin-supply for GPIO
and Fixed regulators") we must ensure the parent nodes of a regulator
are present in DT if they are described in the vin-supply property
For the am65x reference board the DRAM chips are fed by the 3v3 rail
which is fed by the main 12v rail. Add the bootph properties to these DT
nodes to prevent them from being pruned during the SPL build so we can
enable power to the DRAM chips
Signed-off-by: Bryan Brattlof <[email protected]>
Tested-by: Nishanth Menon <[email protected]>
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There are multiple version of the same reference board with different
RAM size and it's not enough to base the RAM size entirely from DT. To
better support it use the get_ram_size way to scan for the actual RAM
size of Airoha SoC and increase the size of the memory map.
Also rework the memory map to account for 2 memory map. The first one of
2GB for 32bit DMA and for safe usage of U-Boot. The second one for the
rest of the RAM since up to 8GB are supported.
Reviewed-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Christian Marangi <[email protected]>
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Switch to OF_UPSTREAM to make use of the upstream devicetree.
Signed-off-by: Frieder Schrempf <[email protected]>
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Probe the USB hub on the BL i.MX8MM OSM-S board.
Signed-off-by: Frieder Schrempf <[email protected]>
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Enable everything that is required to load via USB. The SPL needs
SDP support so it can load the U-Boot proper image via USB after
it has been loaded via serial loader mode of the i.MX.
This way we can use the uuu tool for loading SPL and U-Boot
proper like this:
uuu -brun flash.bin
Signed-off-by: Frieder Schrempf <[email protected]>
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Merge the outstanding changes from the 'next' branch to master.
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While we continue to have some systems which support extremely legacy
OS booting methods, we do not have use cases for supporting this in
Falcon mode anymore. Remove this support and references from the
documentation.
Co-developed-by: Anshul Dalal <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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mmu_status is used in io memcpy functions to prevent accesses to non
8-byte aligned addresses when the mmu is disabled. Though there is a
redundant definition enabled when icaches is turned off by setting
SYS_ICACHE_OFF.
This patch removes the redundant definition, allowing mmu_status to
properly report the status regardless of config settings. This shouldn't
be a problem since access to non 8-byte aligned data can be done
irrespective of icache state.
Fixes: 268f6ac1f95c ("arm64: Update memcpy_{from, to}io() helpers")
Signed-off-by: Anshul Dalal <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* DDR updates:
- IOSSM mailbox compatibility check
- Correct DDR calibration status handling
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
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Use the ARM64 kernel booting register settings, defined in Linux
documentation Documentation/arch/arm64/booting.rst:
x0 = physical address of device tree blob (dtb) in system RAM.
so kernel can replace U-Boot in FIP without modification of BL31.
Use x0 for future TF-A version and keep x2 as fallback to be compatible
with previous version of TF-A BL31.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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USB 3.1 node is enabled for Agilex5.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.
Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).
Without this check, builds with dcache disabled will fail to compile.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.
Signed-off-by: Mahesh Rao <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.
Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.
This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Change is to allow the user to choose speed and mode values
from dts or the default ones.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add NAND node to the base stratix10 dtsi file.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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In order to circumvent CCU NOC issue in Agilex5, it is recommended
to disable cache allocation for reads. This prevents hang issues
caused by CCP (Common Cache Pipe) Fill Done FIFO overflow.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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This series from Debbie Horsfall <[email protected]> enhances the
Vexpress64 platform in a few ways.
Link: https://lore.kernel.org/r/[email protected]
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