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Enable multiple storages for u-boot env:
MMC or SPI flash or NOWHERE for usb
so u-boot can runtime select the storage flash according to boot device.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The TEE memory should be reserved when TEE is present, so need
to runtime update dram bank and memory information according to
tee present or not.
Signed-off-by: Ji Luo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
know A35 reset and reinitialize rpmsg.
Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
M33 will always receive interrupt.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Dynamic setting mmcdev and mmcroot.
Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"
Signed-off-by: Peng Fan <[email protected]>
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Add ahab_dump_buffer API to dump AHAB buffer for debug purpose
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add ahab_release_caam() function to the S400 API.
Signed-off-by: Clement Faure <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Assign the LPAV owner to RTD, and assign LPAV masters and peripherals
to APD. So except the masters and peripherals, other resources
(like DDR, cgc2, pcc5) in LPAV won't be reset during reboot and suspend.
No needs to initialize DDR again after reboot.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.
And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When reset with dual boot mode, the LPAV domain won't power down
due to its master is not assigned to APD. So the NICLPAV keeps the
last setting to use PLL4PFD1. So before SPL initialize the PLL4,
we need to switch NICLPAV to FRO192, otherwise system will hang.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add CAAM clock entry in PCC3
Signed-off-by: Peng Fan <[email protected]>
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Add i3c controller clock enable/disable function for imx8ulp.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Clark Wang <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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With this change, we no need to include pcc/cgc header files both.
Signed-off-by: Peng Fan <[email protected]>
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Some printf() have strings that doesn't terminate with end of line
and make the output hard to read.
Signed-off-by: Clément Péron <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Add pwm1/backlight support nodes for imx8mm_evk board
Signed-off-by: Tommaso Merciai <[email protected]>
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Add pwm_regs struct for i.MX8MM SOC
Signed-off-by: Tommaso Merciai <[email protected]>
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Add pwm control registers fields defines into imx-regs.h:
- prescaler
- dozeen
- waiten
- dbgen
- clksrc_ipg_high
- clksrc_ipg, en field
References:
- iMX8MMRM.pdf p 3884
Signed-off-by: Tommaso Merciai <[email protected]>
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Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Disable SPL exception vector which causes issue to ROM patch execution
when SPL calling ROM API.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Conversion to DM_SERIAL is mandatory.
Select DM_SERIAL and add a imx6q-tbs2910-u-boot.dtsi file
that describes the nodes that require dm-pre-reloc, which allows
the DM model to configure the UART pinctrl early.
Remove the now unneeded board UART initialization.
Signed-off-by: Fabio Estevam <[email protected]>
Tested-by: Soeren Moch <[email protected]>
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With DM_SERIAL selected, it is no longer needed board code to
initialize the UART.
Describe the nodes that require dm-pre-reloc, which allows
the DM model to configure the UART pinctrl early.
Remove the now unneeded board UART initialization.
Signed-off-by: Fabio Estevam <[email protected]>
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Configure binman ATF blob entry type to use the path from the BL31
environment variable, if defined.
Signed-off-by: Ariel D'Alessandro <[email protected]>
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Add settings for operating PLL at 933 MHz. This setting is useful in
case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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The correct compatible string for i.MX8MP variant of DWC EQoS MAC
is "nxp,imx8mp-dwmac-eqos", use it. Drop the two current users of
the current wrong compatible string to avoid breaking them.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marcel Ziswiler <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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To be in sync with the linux devicetree add the disable-smarteee
property.
Signed-off-by: Heiko Thiery <[email protected]>
Tested-by: Marek Vasut <[email protected]> # 8MNANOD4-EVK
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To be in sync with the linux devicetree change the 'phy-reset-gpios' in
the fec node to 'reset-gpios' in the phy node. The PHY reset will be
done by the eth-phy-uclass driver while probing the PHY. This is ok
since it is done before probing the fec.
Signed-off-by: Heiko Thiery <[email protected]>
Tested-by: Marek Vasut <[email protected]> # 8MNANOD4-EVK
Reviewed-by: Fabio Estevam <[email protected]>
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With the correct settings described in the device-tree the PHY settings
in the board init are no longer required. The values are taken from the
linux device tree.
The PHY latency settings are derived from the phy-mode property and the
voltage seetings are done via the regulator.
Suggested-by: Michael Walle <[email protected]>
Signed-off-by: Heiko Thiery <[email protected]>
Tested-by: Marek Vasut <[email protected]> # 8MNANOD4-EVK
Reviewed-by: Fabio Estevam <[email protected]>
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removed sec_init() call from board files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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device tree imported from linux kernel.
c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.
removed sec_init() call from board files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
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LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Signed-off-by: Horia Geantă <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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i.MX7D - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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i.MX6,i.MX6SX,i.MX6UL - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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i.MX8MM/MN/MP/MQ - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Ye Li <[email protected]>
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MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.
Without this delays in R5 SPL are 10x off.
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the
"phy-mode" / "phy-connection-type" property. Add corresponding UT test.
Use them treewide.
This allows us to inline the phy_get_interface_by_name() into
ofnode_read_phy_mode(), since the former is not used anymore.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
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Add helpers ofnode_get_phy_node() and dev_get_phy_node() and use it in
net/mdio-uclass.c function dm_eth_connect_phy_handle(). Also add
corresponding UT test.
This is useful because other part's of U-Boot may want to get PHY ofnode
without connecting a PHY.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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There are no platforms for this architecture anymore, remove unused
code.
Signed-off-by: Tom Rini <[email protected]>
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Based on current usage, migrate a number of DP-DDR related options to
Kconfig.
Cc: Priyanka Jain <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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As no platforms override this value, set it for all mpc83xx platforms.
Cc: Mario Six <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Move this value to the board Kconfig file.
Signed-off-by: Tom Rini <[email protected]>
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Move these two options to the arch Kconfig file.
Cc: Michal Simek <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Michal Simek <[email protected]>
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This symbol is only possibly useful on some mvebu platforms, so move the
symbol there and select it for the only current user.
Cc: Mario Six <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This is a little tricky since SoCFPGA has code to determine this as
runtime. Introduce a guard variable for platforms to select if they
have a static value to use. Then for ARCH_SOCFPGA, call
cm_get_qspi_controller_clk_hz() and otherwise continue the previous
behavior.
Cc: Jagan Teki <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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