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The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.
This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.
Signed-off-by: Christoph Niedermaier <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Christoph Niedermaier <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:
- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot
Signed-off-by: Ariel D'Alessandro <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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The FXL6408 GPIO expander manages critical devices,
including on-module USB hub. Configure the expander to
switch the USB hub into bypass mode, allowing to use
on-carrier-board USB hub.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
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Extension boards can be added to Compulab's iot-gate-imx8mm.
We implement extension board manager for detecting the extension
boards.
Signed-off-by: Uri Mashiach <[email protected]>
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: uboot-imx <[email protected]>
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add the following overlays:
- IED extension board
- CAN/TPM/ADC extension board on IED board.
Signed-off-by: Uri Mashiach <[email protected]>
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
Cc: uboot-imx <[email protected]>
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Obatin the SoC current temperature in print_cpuinfo().
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.
And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Get the MAC address from fuse bank5 word 3 and 4. It has
MSB first at lowest address, so have a reverse order with other
iMX used in mac.c
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.
A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Remove the freescale vendor name from CPU revision print to align
with other i.MX platforms
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The setting does not have effect because we should set it after
power on the PS16 for NIC AV.
So move it after upower_init which has powered on all PS
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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To avoid DCNANO underrun issue on high loading test, set its
read Qos on NIC_LPAV to highest
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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For singel boot, set flexspi0 mem to be accessed by A35
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not
able to receive interrupts from the modules.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.
Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Change boot device logic to also allow environment stored in fat and in
ext4 when booting from SD or from eMMC.
As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location
to use IS_ENABLED instead for all modes, returning NOWHERE when no valid
mode is found.
Signed-off-by: Ricardo Salveti <[email protected]>
Reviewed-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Correct printf format for unsigned long long is %llx and not %llxx.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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The imx28 uses following voltage supplies hierarchy:
VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM
\-----> VDDD
One shall first enable DCDC on the parent source (VDDIO) and then
follow with its children.
Signed-off-by: Lukasz Majewski <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Fix the invalid gw7902 M2_RST# gpio pinmux.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add EA iMX7ULP COM board support for building SPL.
Signed-off-by: Ricardo Salveti <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
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Force selecting features present in SoC i.MX7ULP.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.
At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.
Signed-off-by: Heiko Thiery <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Output the secure boot configuration to the console.
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Non GMAC's MDIO pins should have slew rate disabled for R(G)MII modes. Set
them accordingly in DT.
Signed-off-by: Codrin Ciubotariu <[email protected]>
Tested-by: Eugen Hristev <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
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This is the promised second part of the sunxi PR for 2022.04, albeit
technially outside of the merge window. We were working on this full
steam since the beginning of the year, and it deserves to be merged,
I think.
The main attraction is support for the F1C100s SoC, which sports a
venerable ARM926 core. Support for this SoC and the LicheePi Nano board
has been in Linux for years, and U-Boot patches were posted mid last
year already.
The new SoC using ARMv5 also means that the bulk of the new code should
not touch any existing boards, although we did some refactorings first,
of course, which actually cleans up some existing sunxi code.
Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1,
OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards,
including F1C100s and F1C200s devices.
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Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Add support for F1C100s internal dram controller.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Some Allwinner SoCs use ARM926EJ-S core.
Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.
Port this to ARM926EJ-S start code.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.
The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.
Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.
This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.
We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.
This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).
In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.
This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.
Signed-off-by: Andre Przywara <[email protected]>
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So far all Allwinner based boards were doing some not-so-lowlevel-setup
in lowlevel's s_init() routine.
This includes the initial clock, timer and pinmux setup, among other
things. This is clearly out of the "absolute bare minimum to get started"
scope that lowlevel_init.S suggests for this function.
Since we have an SPL, which is called right after s_init(), move those
calls to our board_init_f() function. As we overwrite this only for
the SPL, this has the added benefit of not doing this setup *again*
shortly afterwards, when running U-Boot proper.
This makes gpio_init() to be called from the SPL only, so pull this code
into a CONFIG_SPL_BUILD protected part to avoid build warnings.
Reviewed-by: Samuel Holland <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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There is some code that tries to "reset" the SCTLR_ELx register early in
the boot process. The idea seems to be to guarantee some sane settings
that U-Boot actually relies on, for instance running in little-endian
mode, with the MMU off initially.
However the current code has multiple problems:
- For a start, no platform or config defines the symbol that would
enable that code.
- The code itself really only works if the bits that it tries to clear
are already cleared:
- If we run in big-endian mode initially, any previous loads would have
been wrong already. That applies to the (optional) relocation code,
but more prominently to the mask that it uses to clear those bits:
"ldr x1, =0xfdfffffa" looks innocent, but actually involves a memory
access to the literal pool, using the current endianness.
- If we run with the MMU enabled, we are probably doomed already. We
*could* hope that we are running with an identity mapping, but would
need to do some cache maintenance to avoid losing dirty cache lines.
- The idea of doing a read-modify-write of SCTLR is somewhat
questionable to begin with, because as the owner of the current
exception level we should initialise all bits of this register with a
certain fixed value.
- The code is unnecessarily complicated, and the function name is
misspelled.
While those problems *could* admittedly be fixed, the point that is does
not seem to be used at all at the moment tells me we should just remove
this code, and be it to not give a bad example.
If people care, I could introduce some proper SCTLR initialisation code.
We are about to work this out for the boot-wrapper[1] as we speak, but
apparently we got away without doing this in U-Boot ever since, so it
might not be worth the potential trouble.
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
Signed-off-by: Andre Przywara <[email protected]>
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Setting LINUX_KERNEL_IMAGE_HEADER=y attempts to include an ARM64 Linux
kernel image header at the start of both U-Boot proper and SPL binaries.
However, some definitions that the image header uses are not included by
the SPL linker script, resulting in a build error. Include them the way
they are included in U-Boot proper's linker script to fix the error.
Signed-off-by: Alper Nebi Yasak <[email protected]>
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The commit in the Fixes: tag below broke traffic through switch ports
where the SERDES protocol requires in-band autoneg and this requirement
isn't described in the device tree: SGMII, QSGMII, USXGMII (with
2500Base-X, in-band autoneg isn't supported).
The LS1028A-QDS boards are not yet ready for syncing their device trees
with Linux, since Ethernet is missing there (but has been submitted):
https://lore.kernel.org/lkml/[email protected]/
When agreement is reached for the Ethernet support in Linux, there will
be a sync for these boards as well. For now, just enable in-band autoneg
to fix the breakage.
Fixes: e3789a726269 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <[email protected]>
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Allow device trees to be reused between Linux and U-Boot.
The source for these device trees is linux-next as of commit
bd8a9cd624c6 ("arm64: dts: ls1028a-rdb: update copyright"), which was
chosen because some changes needed to be done to the Linux DTs too,
before they could be shared:
https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#m6f63c92e75fa79a01144b2c2c6dc4776e7971395
There are two more commits on the RDB device tree which haven't been
picked up yet, because they have dependencies on the SoC device tree:
dd3d936a1b17 ("arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source")
b2e2d3e02fb6 ("arm64: dts: ls1028a-rdb: enable pwm0")
These will be picked up on the next resync.
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
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Reuse the scheme implemented by the Kontron SL28 boards in
commit d08011d7f9b4
("arm: dts: ls1028a: disable the PCIe controller by default")
and move the 'status = "okay"' lines for the PCIe controllers
inside a separate U-Boot dtsi for the LS1028A-RDB board. This way, the
existing Linux device tree can simply be dropped in.
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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There is no I2C peripheral on these buses on the reference design board,
and the Linux device tree does not enable them either.
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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There is no SPI peripheral on the LS1028A-RDB, therefore no reason to
enable these nodes in the U-Boot device tree (and Linux does not enable
them either).
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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