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Replace upper-case hex with lower-case hex for address.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace upper-case hex with lower-case hex for address.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace upper-case hex with lower-case hex for address.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace upper-case hex with lower-case hex for address.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Replace upper-case hex with lower-case hex for address.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Prepare v2022.01-rc3
Signed-off-by: Tom Rini <[email protected]>
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These functions currently lack tests so add some. The error handling
differs betwee livetree and flattree at present, so only check the error
codes with livetree.
Signed-off-by: Simon Glass <[email protected]>
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Add the opposite of mapping, so that we can unmap and avoid running out of
address space.
Signed-off-by: Simon Glass <[email protected]>
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efi_system_reset() should exit if called with EFI_RESET_SHUTDOWN.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The eth aliases are for correct probing order, so that each Ethernet
port will get a predictable MAC address from the environment.
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Add node for pioC.
Signed-off-by: Mihai Sain <[email protected]>
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In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the
relocation. The code still has to set up new_gd pointer and new
stack pointer.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Tom Rini <[email protected]>
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Add and Enable USB SuperSpeed Host Port in SPL.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
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Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
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Add ACRY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
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Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.
Signed-off-by: Chia-Wei Wang <[email protected]>
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Add HACE DTS node and enable it for AST2600 EVB.
Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Chia-Wei Wang <[email protected]>
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Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.
Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Chia-Wei Wang <[email protected]>
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The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
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Some boards do not enable SPL_SERIAL so cannot use the debug UART. Add
this condition to the code and drop use of the preprocessor while we are
here.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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At present we don't init the debug UART in the generic ARM code, but
instead leave it to individual machines to handle. This is not the
way it is supposed to work.
Add the required init to the crt files. This ensures that the UART
is available as early as possible and that the announcement appears
when it should, if enabled.
Signed-off-by: Simon Glass <[email protected]>
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This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.
Signed-off-by: Mark Kettenis <[email protected]>
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- Rename "tqc" to "tq" and related updates
- Assorted minor ARM updates, build updates and documentation updates
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.01-rc3
sdhci:
- Fix emmc mini case with missing firmware interface
zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable
firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location
spi:
- gqsi: Fix write issue at low frequencies
net:
- gem: Disable broadcasts
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Remove the extra (empty) argument passed to str8w, causing the following
error:
<instantiation>:40:47: error: too many positional arguments
str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
^
u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation
17: forward_copy_shift pull=16 push=16
^
Note: no functional change intended.
Fixes: d8834a1323af ("arm: Use optimized memcpy and memset from linux")
Signed-off-by: Pierre-Clément Tosi <[email protected]>
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"TQ-Systems" is written with a dash.
Signed-off-by: Matthias Schiffer <[email protected]>
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The subdivision name "TQ Components" hasn't been in use for a long time.
Rename the vendor directory to "tq", which also matches our Device Tree
vendor prefix.
Signed-off-by: Matthias Schiffer <[email protected]>
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This symbol has been functionally dead for a long time. Remove the last
and recent re-introductions of setting it, and update the whitelist so
it will not be re-introduced again.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_FSL_LAYERSCAPE
Signed-off-by: Tom Rini <[email protected]>
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Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") has
broken boot on chiliboard platform, as it requires '/chosen/tick-timer'
in device-tree. This resulted in following panic message:
Could not initialize timer (err -19)
Provide missing chosen property in device-tree to fix chiliboard
support.
Signed-off-by: Marcin Niestroj <[email protected]>
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- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring
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https://source.denx.de/u-boot/custodians/u-boot-stm
- DHSOM update:
- Remove nWP GPIO hog
- Increase SF bus frequency to 50Mhz and enable SFDP
- Disable video output for DHSOM
- Disable EFI
- Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
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We should avoid #ifdef in C modules and the unused functions
are eliminated by the linker.
Use the more readable IS_ENABLE() instead.
Signed-off-by: Patrick Delaunay <[email protected]>
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In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.
This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.
This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.
Reported-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig
- always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI
and CONFIG_CPU_V7_HAS_NONSEC
- CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig
- the correct sysreset driver is activated in each defconfig:
CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON
Reported-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Currently the upper OTP (after 57) are shadowed in U-Boot proper,
when TFABOOT is not used.
This choice cause an issue when U-Boot is not executed after SPL,
so this BSEC initialization is moved in SPL and no more executed in U-Boot,
so it is still executed only one time.
After this patch this BSEC initialization is done in FSBL: SPL or TF-A.
To force this initialization in all the case, the probe of the BSEC
driver is forced in SPL in the arch st32mp function: spl_board_init().
Even if today BSEC driver is already probed in STM32MP15x clock driver
clk_stm32mp1.c because get_cpu_type() is called in
stm32mp1_get_max_opp_freq() function.
Reported-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot
used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated
in 1-1-4 mode, the hog has adverse effects and causes transfer corruption,
since the hogged pin is also the IO2 pin. Remove the hogs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.
This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Device tree alignment with Linux kernel v5.15-rc6
- Set {bitclock,frame}-master phandles on ST DKx
- Add coprocessor detach mbox on stm32mp15x-dkx boards
- Add coprocessor detach mbox on stm32mp157c-ed1 board
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Use binman to add the stm32image header on SPL binary for basic boot
or on U-Boot binary when it is required, i.e. for TF-A boot without FIP
support, when CONFIG_STM32MP15x_STM32IMAGE is activated.
The "binman" tool is the recommended tool for specific image generation.
This patch allows to suppress the config.mk file and it is a preliminary
step to manage FIT generation with binman.
The init_r parsing of U-Boot device tree to search the binman
information is not required for STM32MP15, so the binman library
can be removed in U-Boot (CONFIG_BINMAN_FDT is deactivated).
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The missing trailing newline could confuse check-config.sh if the
definition of an option was on the first line of the next file that
find(1) happened to return.
Signed-off-by: William Grant <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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[trini: Migrate CONFIG_EXYNOS7420 as part of merging, so espresso7420
still builds]
Signed-off-by: Tom Rini <[email protected]>
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Don't use efi_allocate_pages(). The allocated memory isn't carved out of
the lmb allocations. The memory might then be allocated twice.
Particulary, this might happened with the fdt_high/initrd_high feature
which will relocate the fdt/ramdisk. This might then overlap with the
spin table.
Instead use memalign() which allocates on memory on the heap which is
correctly carved out by lmb.
Please note, that the memory is later reserved in the device tree as
well as in the EFI memory map in ft_fixup_cpu() (in
arch/arm/cpu/armv8/fsl-layerscape/fdt.c).
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Instead of looking at all USB (host) devices, just search all DWC3
device tree nodes. This will (1) fix a panic if of_match is zero and (2)
also apply the fixup if the controller is in peripheral mode. Both
happen when the DWC3 USB controller driver is used.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Copy the board device tree files from linux v5.14. On top of the v5.14
dtbs the changes of these two patches are included here which are needed
for u-boot:
https://lore.kernel.org/linux-devicetree/[email protected]/
https://lore.kernel.org/linux-devicetree/[email protected]/
At the time of this writing the patches were accepted and will be
included in 5.15.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
linux kernel v5.14.12.
Notable changes:
- second watchdog added
- the number of chip selects of the SPI controller is now correct and
reflects what the hardware offers
- the LPUARTs have the correct clock parent
- USB controllers are enabled by default, which was already the case
before this sync because all board enabled all the USB controller
nodes. A linux patch to fix this is pending.
- the eSDHC controller changes from big-endian to little-endian, but
that property seems to be not used at all.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Disable the PCIe controllers by default, just like in the linux device
tree. But there is one catch, for linux they are enabled in-place by the
bootloader. Obviously, this doesn't work for the bootloader. Thus we
explicitly enable the controllers in the -u-boot.dtsi files.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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To make the synchronization of the u-boot device tree with the one from
linux easier, move the I/O window to the one which is specified in the
linux device tree. The actual value shouldn't matter as long as it
mapped to the corresponding memory window of the PCIe controller which
is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h
(second controller).
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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This property is unused in the layerscape PCIe controller driver and not
present in the linux device tree. Remove it to be similarly.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
compatible = "fsl,ls1028a-pcie";
Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.
Cc: Hou Zhiqiang <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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