summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2021-08-26arm64: zynqmp: Fix node name for ds35/36 ledsMichal Simek
By dt-binding specs led nodes should have -led suffix that's why add it. Signed-off-by: Michal Simek <[email protected]>
2021-08-25arm: socfpga: Enable Intel N5X device buildSiew Chin Lim
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-25arm: dts: Add base dtsi and devkit dts for Intel N5X deviceSiew Chin Lim
Add device tree for N5X. Signed-off-by: Siew Chin Lim <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Ley Foon Tan <[email protected]>
2021-08-25arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim
Add SPL for N5X. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]>
2021-08-25arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-25arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-25arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim
Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-25arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim
Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-24ARM: rmobile: beacon-renesom: Enable QSPI NOR FlashAdam Ford
There is a QSPI NOR flash part on the board. Because this chip isn't yet supported in Linux, but it is supported in U-Boot, and the face that the RPC_SPI compatible names are different in U-Boot and Linux, the device tree updates are confined to -u-boot.dtsi files. In order to use the QSPI, TF-A must leave RPC unlocked by compiling TF-A with RZG_RPC_HYPERFLASH_LOCKED=0. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Biju Bas <[email protected]>
2021-08-24arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee
N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]>
2021-08-24arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-24arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim
Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-24arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim
function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <[email protected]>
2021-08-23Merge tag 'efi-2021-10-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc3 Documentation: * Rename Freescale to NXP * Document structures used for the UEFI TCG2 protocol UEFI: * Device paths must use EfiBootServicesData
2021-08-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot for Layerscape Boards like lx2, sl28, ls2088ardb. powerpc: Fixes for t208xrdb revd board and cortina related configs update for T208xRDB, T4240RDB.
2021-08-22bootcount: add a new driver with syscon as backendNandor Han
The driver will use a syscon regmap as backend and supports both 16 and 32 size value. The value will be stored in the CPU's endianness. Signed-off-by: Nandor Han <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2021-08-18armv8: fsl : create bootcmd and mcinitcmd as per boot sourceWasim Khan
NXP platforms expect custom bootcmd and mcinitcmd to be updated as per boot source with default environment. Check env variable fsl_bootcmd_mcinitcmd_set to prepare bootcmd and mcinitcmd Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A) Signed-off-by: Wasim Khan <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2021-08-18board: sl28: drop unneeded and outdated flash partitionsMichael Walle
This board doesn't use the MTD subsystem in u-boot, thus there is no need to specify the partitions. They are outdated anyway. Just drop them. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2021-08-18arm: Finish migration of HAS_FSL_XHCI_USBTom Rini
This symbol was largely migrated, except for one case. Update it. Cc: Priyanka Jain <[email protected]> Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
2021-08-17efi_loader rename enum efi_mem_type to efi_memory_typeHeinrich Schuchardt
Use the same name as in the UEFI specification to avoid confusion. Signed-off-by: Heinrich Schuchardt <[email protected]>
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li
Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Bin Meng <[email protected]>
2021-08-16arm: stm32mp1: Implement ECDSA signature verificationAlexandru Gagniuc
The STM32MP ROM provides several service. One of them is the ability to verify ecdsa256 signatures. Hook the ROM API into the ECDSA uclass. Signed-off-by: Alexandru Gagniuc <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2021-08-16ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex for SPL, so opt for the second option. This incurs 20ms delay during boot, when SPL loads U-Boot to DRAM. Signed-off-by: Marek Vasut <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16arm: dts: stm32mp15: alignment with v5.14Patrick Delaunay
Device tree alignment with Linux kernel v5.14-rc3 - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 - ARM: dts: stm32: add a new DCMI pins group on stm32mp15 - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16stm32mp: correctly handle board_get_usable_ram_top(0)Patrick Delaunay
The function board_get_usable_ram_top can be called after relocation with total_size = 0 to get the uppermost pointer that is valid to access in U-Boot. When total_size = 0, the reserved memory should be not take in account with lmb library and 'gd->ram_base + gd->ram_size' can be used. It is the case today in lib/efi_loader/efi_memory.c:efi_add_known_memory() and this patch avoids that the reserved memory for OP-TEE is not part of the EFI available memory regions. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIPPatrick Delaunay
The MTD tee partitions used to save the OP-TEE binary are needed when TF-A doesn't use the FIP container to load binaries. This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated code in U-Boot binary and prepare the code cleanup when CONFIG_STM32MP15x_STM32IMAGE support will be removed after TF-A migration to FIP support. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16arm: stm32mp: add defconfig for trusted boot with FIPPatrick Delaunay
Add TF-A FIP support for trusted boot on STM32MP15x, when STM32MP15x_STM32IMAGE is not activated. With FIP support the SSBL partition is named "fip" and its size is 4MB, so the ENV partition name in device tree (for SD card or eMMC) or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND) need to be modified. With FIP the TEE MTD partitions are removed because the OP-TEE binray are included in the FIP containers. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16arm: stm32mp: handle the OP-TEE nodes in DT with FIP supportPatrick Delaunay
With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE is not activated), the DT nodes needed by OP-TEE are added by OP-TEE firmware in U-Boot device tree, present in FIP. These nodes are only required in trusted boot, when TF-A load the file u-boot.stm32, including the U-Boot device tree with STM32IMAGE header, in this case OP-TEE can't update the U-Boot device tree. Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present in U-Boot device tree only when needed the function stm32_fdt_disable_optee can be removed. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-16arm: stm32mp: add config for STM32IMAGE supportPatrick Delaunay
By default for trusted boot with TF-A, U-Boot (u-boot-nodtb) is located in FIP container with its device tree and with the secure monitor (provided by TF-A or OP-TEE). The FIP file is loaded by TF-A BL2 and each components is extracted at the final location. This patch add CONFIG_STM32MP15x_STM32IMAGE to request the STM32 image generation for SOC STM32MP15x when FIP container is not used (u-boot.stm32 is loaded by TF-A as done previously to keep the backward compatibility). Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-08-14efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt
Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. MajorImageVersion = 1 indicates a kernel that can consume the EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with our initrddump.efi tool. Signed-off-by: Heinrich Schuchardt <[email protected]>
2021-08-12Merge tag 'u-boot-rockchip-20210812' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Rockchip SFC driver support; - DTS sync from kernel; - emmc hs400 support for rk3399; - Fix for spinore bootdevice and MMC boot order;
2021-08-12rockchip: px30: add support for SFC for Odroid Go AdvanceChris Morgan
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <[email protected]> Signed-off-by: Jon Lin <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12rockchip: px30: add the serial flash controllerChris Morgan
Add the serial flash controller to the devicetree for the PX30. Signed-off-by: Chris Morgan <[email protected]> Signed-off-by: Jon Lin <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12rockchip: px30: Add support for using SFCChris Morgan
This patch adds support for setting the correct pin configuration for the Rockchip Serial Flash Controller found on the PX30. Signed-off-by: Chris Morgan <[email protected]> Signed-off-by: Jon Lin <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12rockchip: Fix u-boot-rockchip.bin buildJohan Gunnarsson
Currently there are a few arm32 rockchip board configs that don't generate u-boot-rockchip.bin when running make because CONFIG_BINMAN is not enabled. This patch changes CONFIG_ARCH_ROCKCHIP to also select CONFIG_BINMAN if CONFIG_SPL and !CONFIG_ARM64. Example builds that don't generate u-boot-rockchip.bin without this patch: export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make kylin-rk3036_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make rock_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make tinker-rk3288_defconfig make Signed-off-by: Johan Gunnarsson <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12arm: dts: sync the Rockhip 3368 SoCs from LinuxPeter Robinson
Sync the rk3368 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12arm: dts: sync the Rockhip 3328 SoCs from LinuxPeter Robinson
Sync the rk3328 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-12arm: dts: sync the Rockhip 3399 SoCs from LinuxPeter Robinson
Sync the rk3399 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <[email protected]> (Remove the conflict content for vmarc-som) Signed-off-by: Kever Yang <[email protected]>
2021-08-11Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony) - mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel) - mvebu: sata_mv: Fix HDD identication during cold start (Tony) - a37xx: pci: Fix handling PIO config error responses (Pavel) - Other minor misc changes and board maintainer updates
2021-08-11Merge tag 'u-boot-amlogic-20210810' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic - odroid-n2: fix fdtfile suffix for n2-plus - sei610 & meson64_android cleanups to prepare android 11 boot support - use Android BCB mechanism for reboot reason instead of HW reboot flag - Switch meson64_android boot flow to use abootimg for A/B, AVB and DTBO support
2021-08-11arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernetXiaobo Tian
Remove the recommended MAC address from the network card. NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC address. Signed-off-by: Xiaobo Tian <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsiXiaobo Tian
The host-index-min property is invalid, so it inherits from the sdmmc definition in dtsi. Signed-off-by: Xiaobo Tian <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11arm64: rk3399: r4s: correct the LEDS label nameXiaobo Tian
Correct the LEDS label name and remove the board type prefix, which is actually unnecessary here, removes the redefined system status LED pin. Signed-off-by: Xiaobo Tian <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11ARM: dts: rockchip: update rk3188-radxarock.dtsJohan Jonker
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file. Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11ARM: dts: rockchip: update rk3188.dtsiJohan Jonker
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file. Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11ARM: dts: rockchip: update rk3xxx.dtsiJohan Jonker
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11rk3399: boot_devices fix spinor node nameArtem Lapkin
Problem: board_spl_was_booted_from return wrong boot_devices[3] value /spi@ff1d0000 and same-as-spl dont work properly for SPINOR flash because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device need parse SPINOR flash node as UCLASS_SPI_FLASH spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ... /spi@ff1d0000 > board_boot_order: could not map node @618 to a boot-device /sdhci@fe330000 > /mmc@fe320000 Solution: just change it to /spi@ff1d0000/flash@0 spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ... /spi@ff1d0000/flash@0 > /sdhci@fe330000 > /mmc@fe320000 Signed-off-by: Artem Lapkin <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2021-08-11arm: mvebu: Hang if ddr3_init() failsPali Rohár
If ddr3_init() fails then DDR was not initialized and we cannot load and execute U-Boot. We cannot continue, we cannot do anything in this case, so hang. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-08-11arm: kirkwood: Do not overwrite CONFIG_SYS_TCLKPali Rohár
Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files to correct SOC/platform value. So do not overwrite it in board config include files. Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses 200 MHz TCLK. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>