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In order to compile code that uses <asm/atomic.h> on sandbox, we must
provide this header. RISC-V shows us today how to do so with the generic
header implementation, so copy that.
Signed-off-by: Tom Rini <[email protected]>
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Normally, local_save_flags is used as part of the local_irq_* macros, so
remove that as it's unused. Make local_irq_save do something to the
passed variable so that it won't trigger unused variable warnings later.
Signed-off-by: Tom Rini <[email protected]>
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If there is an unhandled KCS/BPC pending interrupt after reboot,
the KCS/BPC Linux driver may trigger interrupts immediately upon
registering the irq. However, since the driver is not yet initialized
to handle them, this can lead to unexpected behavior.
To prevent this, disable KCS/BPC interrupts in u-boot to avoid pending
interrupts from being raised before the Linux driver is fully initialized.
Signed-off-by: Stanley Chu <[email protected]>
Signed-off-by: Jim Liu <[email protected]>
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npcm_timer driver is changed to use SECCNT counter.
Signed-off-by: Jim Liu <[email protected]>
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Add pinmux to select the HSYNC signal as the VCD input.
Signed-off-by: Stanley Chu <[email protected]>
Signed-off-by: Jim Liu <[email protected]>
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R-Car V4H Sparrow Hawk board
Retronix R-Car V4H Sparrow Hawk EVTA1 is populated with Spansion S25FS512S,
EVTB1 is populated with Winbond W77Q51NW. Describe the SPI NOR using generic
"jedec,spi-nor" compatible, because both flashes can be auto-detected based
on their built-in IDs.
Signed-off-by: Marek Vasut <[email protected]>
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V4H Sparrow Hawk EVTB1
The Retronix R-Car V4H Sparrow Hawk EVTB1 uses 1V8 IO voltage supply
for VDDQ18_25_AVB power rail. Update the AVB0 pinmux to reflect the
change in IO voltage. Since the VDDQ18_25_AVB power rail is shared,
all four AVB0, AVB1, AVB2, TSN0 PFC/GPIO POC[7..4] registers have to
be configured the same way.
Correct the voltage for EVTA1 boards accordingly by patching the U-Boot
control DT in SPL.
Signed-off-by: Marek Vasut <[email protected]>
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R-Car V4H Sparrow Hawk EVTB1
Invert the polarity of microSD voltage selector on Retronix R-Car V4H
Sparrow Hawk board. The voltage selector was not populated on prototype
EVTA1 boards, and is implemented slightly different on EVTB1 boards. As
the EVTA1 boards are from a limited run and generally not available,
update the DT to make it compatible with EVTB1 microSD voltage selector.
Signed-off-by: Marek Vasut <[email protected]>
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There are some drivers which call a "dmb" for a type of sync. Add that
as well to sandbox.
Signed-off-by: Tom Rini <[email protected]>
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Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Introduce the initial device tree support for Andes Voyager board.
We will convert to OF_UPSTREAM once the patch series for kernel is merged.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The Voyager is Andes' first RISC-V development board.
It is built around Qilai SoC,
which includes Andes AX45MP quad-core cluster.
Introduce the Kconfig entry for the Voyager board.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Properties didn't match dt binding that's why should be fixed.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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U-Boot typically can be loaded from different storage media, such as
eMMC, SD card, SPI flash, but also from non-persistent media such as USB
(via proprietary protocols loading directly into SRAM, or fastboot, DFU,
etc..), JTAG, ...
This information is usually reported by the BootROM via some proprietary
mechanism (some specific address in registers/DRAM for example). For
Rockchip, that information is stored in a register
(BROM_BOOTSOURCE_ID_ADDR).
While we already have the information about which medium was used to
load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this
new property represents the medium used to load U-Boot first phase
(depending on configuration, can be VPL/TPL/SPL) which absolutely may
differ from the one used to load U-Boot proper!
It would be useful to know which medium was used to load the first phase
of U-Boot, for example to check fallback mechanisms (proper loaded from
a different medium than first phase) are actually working.
For now, this only applies to Rockchip's U-Boot proper DT but could be
applied to the kernel's as well and possibly for other architectures or
vendors.
Signed-off-by: Quentin Schulz <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364
Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
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In commit 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and
lmb_alloc_base() API's") an additional allocation was mistakenly
introduced resulting in ${kernel_comp_size} containing the address of a
second 64mb region rather than the actual value of KERNEL_COMP_SIZE.
Additionally, in commit b40d7b8f72f1 ("Merge patch series "lmb: use
a single API for all allocations"") merge conflict resulted in an
additional 128mb allocation for ${loadaddr} when CONFIG_FASTBOOT
is enabled, where it should actually be set to the same value as
${fastboot_addr_r} to respect size constraints (and since it doesn't
seem to interfer with any bootflows).
Fixup both of these, freeing up 192mb of memory.
Fixes: 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and lmb_alloc_base() API's")
Fixes: b40d7b8f72f1 ("Merge patch series "lmb: use a single API for all allocations"")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The JEDEC LPDDR3 spec defines mode register 0 (MR0) as being read-only,
so there is no point in trying to set its value.
Also the H616 memory controller encodes the mode register index to be
written starting from bit 8 in MRCTRL1 (for LPDDR3 and LPDDR4 chips), so
we need to OR in that number to tell the controller which MR to program.
On top of that, the mode registers between DDR3 and LPDDR3 are
completely different, so writing values crafted for DDR3 into a LPDDR3
chip is just wrong. Due to the above mentioned bugs the writes for
MR0-MR2 did not have any effect (as they were all trying to set the
read-only MR0), so the mode registers just stayed unchanged.
Looking at the LPDDR3 spec and the BSP code, let's write the proper MR
values into LPDDR3 chips, using the proper addressing mode.
Use the opportunity to document the LPDDR3 mode register bits written.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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Recent changes in the H6 clock code added delay() calls into the SPL clock
setup routine, which requires the timers to work. When compiling for
AArch64, we are always using the Arm Generic Timer (aka. arch timer),
which does not require further setup, hence having an empty timer_init()
routine.
However for 32-bit SoCs we use the Allwinner timers, which require some
setup routine, and hence we need timer_init() to be called before
clock_init().
Swap the order of the two calls, to be more robust when compiling the H6
clock code for AArch32 or when using the Allwinner timers for whatever
reason.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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Variables holding addresses are typically using the "long" C type in
U-Boot, to be easily compatible with both 32-bit and 64-bit builds.
The A133 DRAM driver is typically compiled for AArch64, so u64 is the
same type as unsigned long, but that breaks when compiling the DRAM
driver in AArch32 (for some experiments).
Fix the type to make the code more portable.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.
Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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There is nothing special for u-boot in the V3/V3s device-tree files,
they are just copies of the upstream ones.
Remove the copies and switch to OF_UPSTREAM for supported boards.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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This property is not documented. And the "mediatek,ipm-spi" SPI
driver doesn't check it.
Signed-off-by: Shiji Yang <[email protected]>
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This adds more common functions found on other architectures that will
allow for more compile-testing of drivers. These are either dummy
functions as we do not need them or mappings to existing functions,
similar to how other architectures handle it.
Signed-off-by: Tom Rini <[email protected]>
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As there are no platforms for this SoC, remove the code.
Signed-off-by: Tom Rini <[email protected]>
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watchdogs in U-Boot"
This series from Wadim Egorov <[email protected]> cleans up how
watchdogs are handled on some phytec TI K3 platforms.
Link: https://lore.kernel.org/r/[email protected]
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The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
Signed-off-by: Wadim Egorov <[email protected]>
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The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
Signed-off-by: Wadim Egorov <[email protected]>
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The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
Signed-off-by: Wadim Egorov <[email protected]>
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In order to set the BOOTFILE symbol we first need to have USE_BOOTFILE
be set, or some of the logic might not work as expected later on when
building. Second, defaults like this belong with the symbol itself.
Fixes: da595d236b97 ("include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile")
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314
- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
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Update Makefile to support Agilex7 M-series platform enablement.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Update Kconfig for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex7 M-series reuse the clock driver from Agilex.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file
using bootm command.
Change to use CONFIG_SPL_ATF to differentiate the bootfile of default
environment variable. We shouldn't use CONFIG_FIT because it is enabled
by default for U-Boot Proper.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Handoff settings updated for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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To improve help info for bridge enable/disable command.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add platform related files for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex7 M-series support has been added using upstream Linux DTS.
socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and
Agilex7 M-series platforms.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Migrate the legacy Agilex platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.
This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.
This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.
Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.
Once all SoC64 devices has been successfully transition to clock
driver model method, this implementation will be cleaned up.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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