| Age | Commit message (Collapse) | Author |
|---|
|
This patch adds support for RSA command, performs RSA encrypt &
RSA decrypt on data blob of key size.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
This patch adds support for encryption and decryption on a given data
blob using different key sources such as userkey(KUP), device key and
PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has
been introduced.
Command:
zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n"
Encrypts or decrypts blob of data at src address and puts it\n"
back to dstaddr using key and iv at keyaddr and ivaddr\n"
respectively. keysrc values specifies from which source key\n"
has to be used, it can be User/Device/PUF key. A value of 0\n"
for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
aesop value would specify the operationwhich can be 0 for\n"
decrypt and 1 for encrypt(1) operation\n";
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.
Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.
Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Enable SPI drivers and driver model for microblaze.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
zynq-zturn was checked on V5 board, same error.
Maybe Z-turn board have the same problem (board with W25Q128BVFIG).
Signed-off-by: Alexandre GRIVEAUX <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Implement early init by calling generic board_init_f_alloc_reserve and
board_init_f_init_reserve functions:
* drop SYS_MALLOC_F_LEN related code, as allocation and gd->malloc_base
assignment are taken care of by the generic functions
* drop _gd logic
Cc: Michal Simek <[email protected]>
Signed-off-by: Ovidiu Panait <[email protected]>
|
|
Currently, the exceptions setup code is duplicated in pre-relocation and
post-relocation init. Factor out this code to __setup_exceptions asm
routine to get rid of the duplication.
__setup_exceptions is called with a relocation offset parameter (r5)
which is set to zero for pre-reloc init and gd->reloc_off for post-reloc
exception setup.
Cc: Michal Simek <[email protected]>
Signed-off-by: Ovidiu Panait <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
|
|
Signed-off-by: Pragnesh Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
This matches the naming scheme of other timer drivers.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
This is a regular timer driver, and should live with the other timer
drivers.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
Although the max DMA size supported by the hardware register is 22 bits (or
4M), the Linux driver for this device only supports transfers of up to 2M.
On a device with 8M total memory, I don't think it will make too much of a
difference.
Reported-by: Damien Le Moal <[email protected]>
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE.
OF_SEPARATE may indicate that the user wishes U-Boot to use a different
device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may
also indicate that the device tree which would be obtained via
OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this
latter case, enabling OF_BOARD_FIXUP will result in corruption of the
device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is
configured for S-Mode.
Fixes: 1c17e55594a394ced7de88d91be294eaf8c564c1
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Leo Liang <[email protected]>
|
|
This reverts commit 3a51b2a2c3cedc0d2a9ce981b8e00ab8cefcb6b7.
Signed-off-by: Tom Rini <[email protected]>
|
|
On all newer Layerscape SoCs, only the export-controlled ciphers of the
crypto module are disabled on non-E parts. Thus it doesn't make sense to
completely remove the node. Linux will figure out what is there and what
is not.
Just remove it for older SoCs, where the module is indeed completely
disabled on non-E parts.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Horia Geanta <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
Add basic support for the Kontron SMARC-sAL28 board. This includes just
the bare minimum to be able to bring up the board and boot linux.
For now, the Single and Dual PHY variant is supported. Other variants
will fall back to the basic variant.
In particular, there is no watchdog support for now. This means that you
have to disable the default watchdog, otherwise you'll end up in the
recovery bootloader. See the board README for details.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Tested-by: Heiko Thiery <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: Razvan Ionut Cirjan <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
|
|
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more static scenarios such as hardwired PCI endpoints
that get initialized later in the system setup) that would allow
two things:
- for a SRIOV capable PCI EP identified by its B.D.F specify
the maximum number of VFs that will ever be created for it
- for hot-plug case, specify the B.D.F with which the device
will show up on the PCI bus
More details can be found in the included documentation:
arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra
Signed-off-by: Laurentiu Tudor <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
|
|
- sun8i emac changes (Andre)
- SCP firmware (Samuel)
|
|
This new function, xen_debug_putc(), is intended to be used to
enable CONFIG_DEBUG_UART on xen guest.
Please note that the underlying functionality in Xen is available
only when Xen is configured with !NDEBUG but is much simpler than
a generic HYPERVISOR_console_io().
Signed-off-by: AKASHI Takahiro <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
|
|
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
|
|
As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.
Signed-off-by: Holger Brunck <[email protected]>
CC: Valentin Longchamp <[email protected]>
CC: Heiko Schocher <[email protected]>
CC: Marek Vasut <[email protected]>
CC: Tom Rini <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
|
|
- fix Gen5 enable of EMAC via FPGA
|
|
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a
System Control Processor, or SCP. ARM Trusted Firmware (ATF)
communicates with the SCP over SCPI to implement the PSCI system
suspend, shutdown and reset functionality. Currently, SCP firmware is
optional; the system will boot and run without it, but system suspend
will be unavailable.
Since all communication with the SCP is mediated by ATF, the only thing
U-Boot needs to do is load the firmware into SRAM. The SCP firmware
occupies the last 16KiB of SRAM A2, immediately following ATF.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Since commit d879616e9e64 ("spl: fit: simplify logic for FDT loading for
non-OS boots"), the SPL looks at the "os" properties of FIT images to
determine where to append the FDT.
The "os" property of the "firmware" image also determines how to execute
the next stage of the boot process, as in 1d3790905d9c ("spl: atf:
introduce spl_invoke_atf and make bl31_entry private"). For this reason,
the next stage must be specified in "firmware", not in "loadables".
To support this additional functionality, and to properly model the boot
process, where ATF runs before U-Boot, add the "os" properties and swap
the firmware/loadable images in the FIT image.
Since this description was copied as an example in commit 70248d6a2916
("binman: Support generating FITs with multiple dtbs"), update those
examples as well for correctness and consistency.
Acked-by: Patrick Wildt <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
This consolidates the SoC-specific part at the top of the file to avoid
cluttering it up with preprocessor conditions.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use
binman"), if the BL31 environment variable was not defined, the firmware
would be loaded from a file "bl31.bin" in the current directory. Restore
that behavior by providing that as the default filename in case no entry
arg is provided, which will be the case if the environment variable is
unset.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Nodes should have a blank line separating them from sibling nodes and
properties. Add the necessary lines.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Previously, because we have no source code about the DRAM initialization
of V3s and missing some configurations (delays and MBUS QoS info), our
V3s DRAM initialization sequence is hacked from the H3 one.
As the SDK shipped with PineCube contains source code for V3s libdram,
we can retrieve these information from it and tweak some other magic
bits.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Jagan Teki <[email protected]>
|
|
When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.
This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.
For example with the simple flashlayout file:
Opt Part Name Type Device Offset Binary
- 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32
- 0x03 ssbl Binary none 0x0 u-boot.stm32
P 0x10 kernel System ram0 0xC2000000 uImage.bin
P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb
Fixes: ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
as its value is IP dependent and not arch dependent
No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops").
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.
This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
Without security, in basic boot, the value is equal to STM32_DDR_SIZE.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.
The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines")
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
|
|
- Assorted R-Car Gen3 updates
|
|
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
|
|
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
|
|
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
|
|
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
|
|
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
|
|
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
|
|
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.
Also fixed the alignment issue on R8A774A1 config.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
|
|
Add usb, usb phy, and fixed regulators nodes
Signed-off-by: Chunfeng Yun <[email protected]>
Acked-by: Bin Meng <[email protected]>
|
|
SAM9X60 SiP (System in Package) are added for SoC identification.
Signed-off-by: Nicolas Ferre <[email protected]>
|
|
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi
Signed-off-by: Claudiu Beznea <[email protected]>
|
|
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.
Signed-off-by: Claudiu Beznea <[email protected]>
|
