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Add an entry for USB boot so that U-Boot could be loaded via
the Serial Download Protocol.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Instead of duplicating code implemented by i.MX8M version of arch_misc_init()
in every board, enable CONFIG_ARCH_MISC_INIT and call arch_misc_init() from
spl_board_init(). This removes the duplication. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220919
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CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13500
- Fix imx8mn-beacon-kit-u-boot
- Merged Purism
- imxrt1170 (already merged in u-boot-imx)
- Fixes in crypto FSL
- Toradex : fixes Verdin
- Serial Driver: fixes when not used as console
- DH Boards : fixes + USB
- Fix CONFIG_SYS_MALLOC_F_LEN (Kconfig)
- Add imx6ulz_smm_m2
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This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.
Signed-off-by: Jesse Taube <[email protected]>
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Currently Makefile produces final mpc85xx image when SPL is not used in
custom file u-boot-with-dtb.bin. It is quite confusing name as build
process produce also intermediate file standard file u-boot-dtb.bin (which
is just intermediate and not bootable). Other platforms use u-boot.bin
(UBOOT_BIN) as standard name for final bootable raw image.
So change Makefile rules and binman to produce final bootable file for
mpc85xx also into file u-boot.bin. There is just need for mpc85xx to not
define default rule for u-boot.bin then instruct binman (via DTS file) to
store final image into u-boot.bin (instead of u-boot-with-dtb.bin) and
finally rename target u-boot-with-dtb.bin to u-boot.bin.
With this change are also removed custom Makefile hacks for mpc85xx that it
produced non-standard output file. And also updated documentation.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
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mode
CPLD in load_default mode ignores watchdog reset signal. It does not reset
board when watchdog triggers reset signal.
Detect load_default mode by GPIO7 - LOAD_DEFAULT_N and delete watchdog
max6370 node from device to prevent registering driver for non-working
watchdog.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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P1/P2 RDB boards have external max6370 watchdog connected to CPLD and this
watchdog is not deactivated on board reset. So if it is active during board
reset, it can trigger another reset when CPU is booting U-Boot. To prevent
possible infinite reset loop caused by external watchdog, turn it off
before reset.
Do it via a new board_reset_prepare() callback which is called from
do_reset() function before any reset sequence.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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CPLD's system reset register is buggy and requires workaround in U-Boot.
So use this kind of board reset only when there is no other reset option.
Introduce a new board_reset_last() callback which is last-stage
board-specific reset and implement CPLD's system reset in this new
board_reset_last() callback instead of board_reset() callback.
Fixes: 20fb58fc5a1c ("board: freescale: p1_p2_rdb_pc: Implement board_reset()")
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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If watchdog timer was already set to non-disabled value then it means that
watchdog timer was already activated, has already expired and caused CPU
reset. If this happened then due to CPLD firmware bug, writing to wd_cfg
register has no effect and therefore it is not possible to reactivate
watchdog timer again. Watchdog starts working again after CPU reset via
non-watchdog method.
Implement this workaround (reset CPU when it was reset by watchdog) to make
watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is
connected to CPLD, not to SoC itself.
Note that reset does not occur immediately after calling do_reset(), but
after few ms later as real reset is done by CPLD. So it is normal that
function do_reset() returns. Therefore hangs after calling do_reset() to
prevent CPU execution of the rest U-Boot code.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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CPLD's system reset register on P1/P2 RDB boards is not autocleared after
flipping it. If this register is set to one in 100ms after reset starts
then CPLD triggers another CPU reset.
This means that trying to reset board via CPLD system reset register cause
reboot loop. To prevent this reboot loop, the only workaround is to try to
clear CPLD's system reset register as early as possible. U-Boot is already
doing it in its board_early_init_f() function, which seems to be enough as
register is cleared prior CPLD triggers another reset.
But board_early_init_f() is not called from SPL and therefore usage of SPL
can cause reboot loop.
To prevent reboot loop when using SPL, call board_early_init_f() function
in SPL too. For accessing CPLD memory space it is needed to have CPLD entry
in TLB.
With this change it is possible to trigger board reset via CPLD's system
reset register on P2020 RDB board.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In both the Freescale DDR controller and the SPD spec, bank address bits
are stored as the number of bank address bits minus 2. For example, if a
chip had 8 banks (3 total bank address bits), the value of
bank_addr_bits would be 1. This is rather surprising for users
configuring their memory manually, since they can't set bank_addr_bits
to the actual number of bank address bits. Rectify this.
There is at least one example of this kind of mistake already, in
board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank
address bits, but bank_addr_bits was set to 2, implying 4 bank address
bits. Such a value is reserved in BA_BITS_CS, but I suspect the
controller simply ignores the top bit, making this kind of mistake
harmless, if misleading.
Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support")
Signed-off-by: Sean Anderson <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Now that we are about to enable DM_ETH by default, remove legacy code.
Cc: Alison Wang <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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There is some code here for the legacy non-DM_ETH case, add a guard
around it.
Cc: Priyanka Jain <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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These boards have been orphaned for some time and are behind on various
DM migrations. Remove them.
Cc: Priyanka Jain <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The *aqds* platforms have not been migrated to be able to enable
CONFIG_DM_ETH with CONFIG_FMAN_ENET. Disable CONFIG_FMAN_ENET on these
platforms.
Cc: Mingkai Hu <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Cc: Pramod Kumar <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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To ease maintenance, let's keep only the main mx28evk_defconfig
and remove the other variants that have not been migrated to DM.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Heinrich Schuchardt <[email protected]>
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The LS1043ARDB rev v7.0 board replaces the AQR105 PHY on MAC9 with an
AQR113C PHY. The address of the PHY on the MDIO bus changes from 0x1 to
0x8. Enable CONFIG_OF_BOARD_FIXUP and update both u-boot and Linux device
trees to reflect this change.
Signed-off-by: Camelia Groza <[email protected]>
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caam driver model enabled in spl for secure boot.
fsl_rsa_mod_exp driver enabled in spl for validating uboot image.
Signed-off-by: Gaurav Jain <[email protected]>
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Move this out of the common header and include it only where needed.
Signed-off-by: Simon Glass <[email protected]>
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A large number of files include <flash.h> as it used to be how various
SPI flash related functions were found, or for other reasons entirely.
In order to migrate some further CONFIG symbols to Kconfig we need to
not include flash.h in cases where we don't have a NOR flash of some
sort enabled. Furthermore, in cases where we are in common code and it
doesn't make sense to try and further refactor the code itself in to new
files we need to guard this inclusion.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_FLASH_CFI_LEGACY
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_FLASH_ERASE_TOUT
CONFIG_SYS_FLASH_LOCK_TOUT
CONFIG_SYS_FLASH_UNLOCK_TOUT
CONFIG_SYS_FLASH_WRITE_TOUT
In practice, for two m68k platforms we move to hard-coding with a
comment the timeout values, rather than try and make convoluted Kconfig
logic. We add options for the write and erase options to the pic32
flash driver, as this driver does make use of them. Everywhere else
these are unreferenced values.
Signed-off-by: Tom Rini <[email protected]>
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All platforms today define CONFIG_SYS_DDR_RAW_TIMING, so drop the code
for this option being unset.
Cc: Qiang Zhao <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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We have a number of CONFIG_SYS_xxx_SIZE options to describe the amount
main memory available. Rework CONFIG_SYS_DDR_SIZE, which described a
size in number of MiB to use CONFIG_SYS_SDRAM_SIZE which is most often
used as a number of bytes. Use shifts of this option when required.
Signed-off-by: Tom Rini <[email protected]>
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On some boards upper 4 bits of i2c boot input data (register 0) are
inverted. Information which bits are inverted is stored in register 2.
So invert read input data back according to register 2 prior processing
them. This fixes printing "rom_loc: value" line during booting.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with
locked lines. P2020 reference manual about L2 memory-mapping mode says:
Accesses to memory-mapped SRAM are cacheable only in the corresponding
e500 L1 caches.
So there is no need to set Caching-Inhibit I-bit for second part of initial
L2 SRAM mapping in TLB entry. Remove it. First part of initial L2 SRAM
mapping already does not have I-bit set.
For more details see also:
https://lore.kernel.org/u-boot/20220508150844.qqxg452rs4wtf5bs@pali/
Signed-off-by: Pali Rohár <[email protected]>
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Add ethernet support
Signed-off-by: Peng Fan <[email protected]>
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Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add basic board codes and defconfig for i.MX93 11x11 EVK board.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Synchronise device tree with linux v5.19-rc5.
Signed-off-by: Marcel Ziswiler <[email protected]>
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Add entry for imx8mm_evk_fspi_defconfig in
board/freescale/imx8mm_evk/MAINTAINERS
Signed-off-by: Mamta Shukla <[email protected]>
Signed-off-by: Thomas Haemmerle <[email protected]>
Tested-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add QSPI Boot option in u-boot-spl for i.MX8m EVK.
Signed-off-by: Mamta Shukla <[email protected]>
Signed-off-by: Thomas Haemmerle <[email protected]>
Tested-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add imx8mm_evk_fspi_defconfig to build QSPI boot image.
This config is based on imx8mm_evk_defconfig with addtional config options to
define FSPI Header parameters required to generate QSPI Header.
Update SPL offset to include header size and overwrite IMX_CONFIG to use
lpddr.cfg for FSPI.
Signed-off-by: Mamta Shukla <[email protected]>
Signed-off-by: Thomas Haemmerle <[email protected]>
Tested-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Andrey Zhizhikin <[email protected]>
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On p1_p2_rdb_pc platforms, we set ddr_data_init to the "poison" value of
0xdeadbeef rather than a real calculated / derived value. Do this
directly and comment rather than via CONFIG.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_PCIE1
CONFIG_PCIE2
CONFIG_PCIE3
CONFIG_PCIE4
CONFIG_PCI1
Signed-off-by: Tom Rini <[email protected]>
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As things stand currently, there is only one PowerPC platform that
enables the options for CHAIN_OF_TRUST. From the board header files,
remove a number of never-set options. Remove board specific values from
arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework
include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for
constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses
to Kconfig.
If any platforms are re-introduced with secure boot support, everything
required should still be here, but now in Kconfig, or requires migration
of an option to Kconfig.
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As
part of this, change fsl_secboot_validate(...) to check that it is
passed a non-empty string, rather than non-NULL.
Cc: Peng Fan <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Kshitiz Varshney <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_ESDHC_DETECT_QUIRK
Signed-off-by: Tom Rini <[email protected]>
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Now that board/freescale/common/Kconfig is safe to be included once,
globally, rename this to arch/Kconfig.nxp to better reflect that it
contains options that are valid on multiple architectures and SoC
families, and not specific to NXP reference platforms either.
Cc: Stefano Babic <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The way that we use this file currently means that we have to guard it
in every platform Kconfig. But it is also required in all NXP
platforms, including non-reference platforms. Make all options in it
have appropriate dependencies so that we can include it a single time
under arch/Kconfig
Signed-off-by: Tom Rini <[email protected]>
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From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card,
Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards.
So address mapping for TDM-PMC card on LBC should not be enabled on any
other P1/P2 RDB board as there is no device at that TDM-PMC address.
Support for P1021RDB and P1025RDB boards was already removed from mainline
U-Boot in commits 6d1dd76afe85 ("board/freescale: Remove P1021RDB board
support") and d521cece5adb ("board/freescale: Remove P1025RDB board
support").
So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and
remove all macros related to TDM-PMC address mappings.
Signed-off-by: Pali Rohár <[email protected]>
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Add #ifdef guard for __SW_BOOT_SD macro like there are guards for all other
__SW_BOOT_* macros.
Signed-off-by: Pali Rohár <[email protected]>
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Signed-off-by: Pali Rohár <[email protected]>
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The only platform currently that defines an ide_preinit function has an
empty one that immediately returns. Remove this hook.
Signed-off-by: Tom Rini <[email protected]>
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These particular code paths aren't used anymore, remove.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_HAS_FSL_DR_USB
Signed-off-by: Tom Rini <[email protected]>
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Merge in v2022.07-rc5.
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This patch adds config support for HDP firmware loading on LS1028A.
Signed-off-by: Oliver Brown <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Yangbo Lu <[email protected]>
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Do board reset via CPLD's system reset register.
Signed-off-by: Pali Rohár <[email protected]>
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