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issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Acked-by: Ian Ray <[email protected]>
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Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Acked-by: Ian Ray <[email protected]>
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Change the PMIC bulk configuration from auto mode to sync mode to avoid
voltage dropout issue seen in auto mode.
Signed-off-by: Ken Lin <[email protected]>
Signed-off-by: Akshay Bhat <[email protected]>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <[email protected]>
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imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Martin Donnelly <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
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Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set.
Signed-off-by: Andrew Shadura <[email protected]>
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On a reset/reboot, the display power needs to be off for atleast 500ms
before turning it back on. So add a delay to the boot process to meet
the display timing requirement.
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
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Setup the LCD backlight brightness control pin to use PWM
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
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To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
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B450v3/B650v3 uses single channel LVDS and does not support HDMI.
B850v3 uses dual channel LVDS and supports HDMI. Hence split the display
setup into two different functions.
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
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Certain pins are not used on the i.MX6, and should have a neutral
pad configuration in order to reduce electrical interference on
the board. This commit defines these pins with a default value
rather than relying on the system defaults.
Signed-off-by: Justin Waters <[email protected]>
Signed-off-by: Akshay Bhat <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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