| Age | Commit message (Collapse) | Author |
|---|
|
Without PS/2 keyboard and mouse in the ASL file, Windows does not
see them. No problem for Linux as it probes keyboard and mouse via
the legacy 8042 I/O port.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Enable ACPI table generation by creating a DSDT table.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Override the default product name U-Boot reports in the SMBIOS
table, to be compatible with the Intel provided UEFI BIOS, as
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
it to do different board level configuration.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Let git ignore dsdt.aml, dsdt.asl.tmp and dsdt.c files.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Enable ACPI table generation by creating a DSDT table for all baytrail
boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
|
|
Quark SoC holds the PCIe controller in reset following a power on.
U-Boot needs to release the PCIe controller from reset. The PCIe
controller (D23:F0/F1) will not be visible in PCI configuration
space and any access to its PCI configuration registers will cause
system hang while it is held in reset.
Enable PCIe controller per Quark firmware writer guide.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Move to driver model for USB and ETH on Intel Bayley Bay.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Since E1000 driver has been converted to driver model, enable it
on Intel Crown Bay. But the Intel Topcliff GbE driver has not been
converted to driver model yet, disable it for now.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
|
|
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.
In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Move to driver model for networking on minnowmax.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Signed-off-by: Gabriel Huau <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR
should be removed.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.
Signed-off-by: Joe Hershberger <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Cc: Tom Rini <[email protected]>
|
|
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE directly.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/<vendor>/Kconfig.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.
Signed-off-by: Jian Luo <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).
Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
|
|
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
|
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
|
