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Add EEPROM detection initialisation for phyCORE-i.MX8MM.
Signed-off-by: Yunus Bas <[email protected]>
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The phyCORE-i.MX 93 is available in various variants (e.g. different ram
sizes, eMMC HS400 yes/no). Enable hardware introspection for the
imx93-phyboard-segin_defconfig, so that during startup the SOM module
variant can be detected, and the hardware can be configured accordingly.
The resulting SPL and u-boot binary shall able to boot each
phyCORE-i.MX 93 module variant on each carrier board. Finally rename
imx93-phyboard-segin_defconfig to imx93-phycore_defconfig, to highlight
its SOM scope.
Signed-off-by: Christoph Stoidner <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Reviewed-by: Yannic Moog <[email protected]>
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The phyCORE-i.MX 93 is available in various variants. Relevant variant
options for the spl/u-boot are:
- with or without HS400 support for the eMMC
- with 1GB ram chip, or 2GB ram chip
The phyCORE's eeprom contains all information about the existing variant
options. Add evaluation of the eeprom data to the spl/u-boot to
enable/disable HS400 and to select the appropriate ram configuration at
startup.
Signed-off-by: Christoph Stoidner <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
Reviewed-by: Yannic Moog <[email protected]>
Tested-by: Primoz Fiser <[email protected]>
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The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram chip.
Add the ram timings for the 2GB chip, in form of a diff compared
to the existing LPDDR4X 1GB timings. With that, the SPL can select the
appropriate timings at startup.
Update also the 1GB ram timings with new version of the DDR Tool.
Signed-off-by: Christoph Stoidner <[email protected]>
Tested-by: Primoz Fiser <[email protected]>
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update MAINTAINERS file, add some more board maintainers.
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Alexander Sverdlin <[email protected]>
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The signal integrity test generates pattern on DDR lines
for certification. The signals must be as fast as possible
and unidirectional.
The test is required from our HW team. The available
u-boot memory test doesn't full fill the our requirements.
The test is planed to be used in all new siemens boards.
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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Add siemens specific memory test. Enable it through Kconfig option
SPL_CMT. The test is required from our HW team. It runs over
temperature during many days:
* must run indefinitively through the *whole* DDR area,
so we cannot use linux memtest for example.
* must write/read/check all values
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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The eeprom contains the information on which module
we are running, so read it from the eeprom and print
it on the console.
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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Get the memory region information from system controller to reduce the
number of platform specific headers. We were aligned on NXP mek board
implementation. This need at least 1 header per memory configuration.
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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Add the HW version read directly from EEPROM.
EEPROM chip data structure is now in a .h file common to draco
and capricorn.
Therefore move out the definitions in draco board to siemens
common place.
From: Alessandro Zini <[email protected]>
Signed-off-by: Alessandro Zini <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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with newest SCFW build_info() works now, so call it
from checkboard() now.
As we only use uart2 as console, do not init uart0.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Alexander Sverdlin <[email protected]>
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sync spl code with 8qxp-mek board.
Signed-off-by: Heiko Schocher <[email protected]>
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sync the image names in imximage.cfg with
the ones used in arch/arm/dts/imx8qxp-u-boot.dtsi
Signed-off-by: Heiko Schocher <[email protected]>
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fix wrong comment.
Signed-off-by: Heiko Schocher <[email protected]>
Reviewed-by: Alexander Sverdlin <[email protected]>
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Boards which use DCD data in SCFW can drop SPL.
We tried in our mainline rework to use this approach
too as other imx8qxp boards do in mainline. But we
failed ... it was a hard way to understand the
reason!
We cannot use DCD image in container as the SCFW
from siemens, does the RAM init on boot itself!
Siemens SCFW reads the RAM config from i2c eeprom and
dependent on this settings, initializes the RAM.
Adding DCD data to the bootcontainer will result in
hang of the SCFW, also DCD data in container image is
static which do not fit our needs.
So we must drop DCD data image, and this has the side
effect that we need SPL, as the task which loads the images
from the container only loads the images to addresses,
and if executed bit is set, starts them.
As now RAM is not initialized from it, and there is no
option to "wait until SCFW has setup RAM", we can only
load SPL into internal RAM at this point, as than SPL
and SCFW boot parallel.
The SPL itself then uses the SCU API to communicate
with the SCFW and it seems that SCFW only responds to
this API requests when RAM setup is already done by the
SCFW, which has a side-effect of a "sync" for the RAM
setup is done by SCFW!
We checked if SPL is always save in accessing RAM for
loading images to it! For tests, we added in our RAM
init part in the SCFW long delays (10 seconds and more)
as we thought there is such a sync missing, and we can
break the board through delaying RAM setup... but we
did not managed to fail booting U-Boot from SPL!
Signed-off-by: Heiko Schocher <[email protected]>
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We have many HW with capricorn i.MX8X boards. The difference in u-boot is
at all by the display of the LEDs.
* put upstream a reference project & board for DT and defconfig
* use the capricorn prefix outside the board/siemens/capricorn folder
Signed-off-by: Enrico Leto <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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probing on capricorn board (imx8qxp based) brings:
Can't find FEC0 clk rate: -19
Cause is that when probing fec_mxc driver, fec_mii_setspeed()
is called which calls fec_get_clk_rate().
fec_mii_setspeed() calls fec_get_clk_rate with NULL pointer
for udev and so as in IMX8QXP case CLK_CCF is enabled
udev gets searched with:
uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
but we do not have yet a UCLASS_ETH ! as we just probing it!
Prevent this by passing udev to fec_get_clk_rate()
Signed-off-by: Heiko Schocher <[email protected]>
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Prepare v2025.01-rc3
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The previous maintainer is no longer involved in total compute.
Signed-off-by: Ben Horgan <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Leo Yan <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc3:
- microblaze:
- Disable JFFS2
- fpga:
- pass compatible flag to fpga_load()
- zynqmp:
- SOM RTC fix
- SC(system controller) PMW polarity fix
- Fix ram_top calculation with introducing XILINX_MINI
- Fix RPU release command
- versal:
- Enable capsule update
- Enable soft reset and Micron octal flashes
- xilinx:
- Align Kconfig regarding SPI_STACKED_PARALLEL
- bootcount:
- Add new zynqmp driver
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There is no common symbol which mini configurations are using and recent
get_mem_top() changes adding 1.3kB without having a way to remove it.
That's why introduce new symbol which can be used for removing features
which are not requested by these configurations.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/aa27b72e17057fa8cbdd92a2bbb863a31c8c1226.1731681053.git.michal.simek@amd.com
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For RTC to start to operate there is a need to call the driver. The simple
way to do it is to set default RTC instance which will call the probe and
do basic initialization.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/01155f1555dbd42adc618906629f5fb45754d5a4.1731419926.git.michal.simek@amd.com
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We are about to add a large number of new entries. Update the prefix to
be a little shorter.
For SMBIOS items, use SYSID_SM_ (for System Management) which is enough
to distinguish it. For now at least, it seems that most items will be
for SMBIOS.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Raymond Mao <[email protected]>
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Enable capsule update in SD boot mode. For getting it work there is a need
to generate or setup dfu_alt_info and enable sysreset with DFU_MMC.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/cede513de764b99560dc3737457dbc8a5cc71d21.1729857366.git.michal.simek@amd.com
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If sysreset is enabled reset_cpu is defined in sysreset uclass that's why
it can't be in platform/board code.
The same change was done by commit f1bc214b0024 ("arm64: zynqmp: Do not
define do_reset() if sysreset is enabled").
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/8c1a5d6148c5e6c46790b725e8148a4e12d393ba.1729857366.git.michal.simek@amd.com
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Use the get_mem_top function to compute the value of ram_top. This was
earlier done through LMB API's, which are no longer available till
after relocation. Use get_mem_top() instead to compute the ram_top
value.
Signed-off-by: Sughosh Ganu <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Wadim Egorov <[email protected]> says:
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.
Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs.
Future K3 SoMs will be able to reuse this logic and overlays.
Link: https://lore.kernel.org/r/[email protected]
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Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.
Signed-off-by: Wadim Egorov <[email protected]>
Acked-by: Neha Malcom Francis <[email protected]>
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qemu_arm64_defconfig with CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=n leads to a
build error:
arch/arm/lib/crt0_64.S:85:
Error: constant expression expected at operand 2 --
`ldr x0,=((CFG_SYS_INIT_RAM_ADDR+CFG_SYS_INIT_RAM_SIZE-480))'
We do not define CFG_SYS_INIT_RAM_ADDR and CFG_SYS_INIT_RAM_SIZE for QEMU.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280
- Add board:
rk3328: FriendlyElec NanoPi R2S Plus
rk3568: Qnap TS433
rk3588: Cool Pi CM5 GenBook
- Move rk3399_force_power_on_reset to TPL for puma board;
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The FriendlyElec NanoPi R2S Plus is a single-board computer based on
Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC,
SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host.
Features tested on a NanoPi R2S Plus 2309:
- SD-card boot
- eMMC boot
- Ethernet
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for Cool Pi GenBook, it works as a carrier board
connect with CM5 SOM.
Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080
Tested by Armbian boot on USB disk.
Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03
Signed-off-by: Andy Yan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Qnap TS433 is a 4-bay NAS based around the RK3568.
Two SATA bays are connected to the RK3568's own SATA controllers while
the other two are connected to a JMicron SATA controller living on the
PCIe bus.
It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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For upstream Linux kernel we use below DTBs for HiHope boards:
- r8a774a1-hihope-rzg2m-ex.dtb
- r8a774e1-hihope-rzg2h-ex.dtb
- r8a774b1-hihope-rzg2n-ex.dtb
Update the CONFIG_OF_LIST to match the above. Now that we have switched
upstream DTS, drop deleting the nodes and also rename the
r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST
files so that the `bootph-all` property gets applied to required nodes
in upstream DTS.
Signed-off-by: Lad Prabhakar <[email protected]>
Signed-off-by: Chris Paterson <[email protected]>
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We are now using the dts/upstream subtree for the RZ/G2L SoC family, so
update the board MAINTAINERS file to match rz-smarc dtsi files in this
subtree.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Improve "mmcautodetect=yes" boot mode autodetection to able to use it
if CONFIG_ENV_IS_NOWHERE=y is used for i.MX9 SoCs and i.MX93 EVK board.
If both CONFIG_ENV_IS_IN_MMC=y and CONFIG_ENV_IS_NOWHERE=y are in the
defconfig, CONFIG_ENV_IS_IN_MMC=y will be overiden default
CONFIG_ENV_IS_NOWHERE settings.
Goal is in this patch to able to use the boot mode autodetection
if defconfig use only CONFIG_ENV_IS_NOWHERE=y option
(without CONFIG_ENV_IS_IN_MMC) for any i.MX9 SoC.
Signed-off-by: Benjamin Szőke <[email protected]>
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DTB should be also placed to DDR. It should be the part of commit
9d688e6da5c9 ("riscv: mbv: Align DT with QEMU").
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Leo Yan <[email protected]> says:
This patch series is to refine the booting on Arm Total Compuate
platform.
It changes to use the info passed in DTB for initialization DRAM info,
and dynamically initializes the booting envoironment variables.
Another big change is to use an envoironment file for boot commands,
based on it, the series extends to support multiple block devices
(MMC and virtio). And the env file is extended for booting Debian.
The last commit is to update memory mapping info based on the DRAM info
passed via DT binding.
Link: https://lore.kernel.org/r/[email protected]
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This commit introduces build_mem_map() function for updating the mem_map
structure with copying info from gd->bd->bi_dram, so that it can keep
the consistence for DRAM info passed via DT.
The page table size is calculated prior to mem_map is ready, introduce
the get_page_table_size() function for a predefined table size.
Signed-off-by: Leo Yan <[email protected]>
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Add booting option for Debian system.
Signed-off-by: Leo Yan <[email protected]>
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Dynamically detect block device in the boot command, this allows to
support both MMC and virtio block devices.
Signed-off-by: Leo Yan <[email protected]>
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Tell the AVB command that is loading from MMC.
Signed-off-by: Boyan Karatotev <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
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The boot command for Total Compute has many aspects and changes from time
to time. So move it to an .env file where it can be a proper script.
Signed-off-by: Boyan Karatotev <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
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Initialize the environment variables 'fdt_addr_r' and 'kernel_addr_r'
during the misc init phase. The static configurations are not needed,
remove them.
Signed-off-by: Boyan Karatotev <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
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On Total Compute, TF-A passes the info via DT binding for the hardware
description - includes the serial, memory, and arm_ffa nodes.
This commit initializes the fdt base address based on the passed the
register x1.
The similar implementation has already been done for the raspberry pi,
so borrow a lot of it.
Co-developed-by: Jackson Cooper-Driver <[email protected]>
Signed-off-by: Jackson Cooper-Driver <[email protected]>
Signed-off-by: Boyan Karatotev <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
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Create an SoC R5 dtsi file that could be used at board level R5 files. This
would help in keeping the SoC level changes in sync across board files.
Signed-off-by: Manorit Chawdhry <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23092
- Implement i.MX93 erratum fix on the dwc_eth_qos driver to fix RMII.
- Add support for Emcraft Systems NavQ+.
- Fix the size of IVT + CSF blob tacked on to u-boot.itb.
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Bastien Curutchet <[email protected]> says:
Hi all,
This patch series aims to add DM support for the AEMIF controller that
can be found in the DaVinci SoCs.
This controller has already a driver used by the Keystone SoCs so I
add my work to it.
As we can now easily import Linux device-trees, I try to stick the
most I can to the Linux bindings of the AEMIF controller. To do so I add
an 'intermediate' driver called 'ti-aemif-cs'. It's in charge of
configuring timings for a given chip select of the AEMIF controller.
Link: https://lore.kernel.org/r/[email protected]
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AEMIF controller is present on other SoCs than the Keystone ones.
Remove Keystone specificities from the driver to be able to use it from
other architectures.
Adapt the ks2_evm/board.c to fit the new driver.
Signed-off-by: Bastien Curutchet <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The Emcraft Systems NavQ+ kit is a mobile robotics platform
based on NXP i.MX8 MPlus SoC.
The following interfaces and devices are enabled:
- eMMC
- Gigabit Ethernet (through eQOS interface)
- SD-Card
- UART console
The device tree file is taken from upstream Linux Kernel
through OF_UPSTREAM
Signed-off-by: Gilles Talis <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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