| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-05-15 | Fix e-mail address of Gary Jennejohn. | Detlev Zundel | |
| Signed-off-by: Detlev Zundel <[email protected]> | |||
| 2008-10-18 | rename CFG_ macros to CONFIG_SYS | Jean-Christophe PLAGNIOL-VILLARD | |
| Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]> | |||
| 2008-08-25 | Correct ARM Versatile Timer Initialization | Gururaja Hebbar K R | |
| - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar <[email protected]> | |||
| 2006-03-13 | Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer and | Wolfgang Denk | |
| cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006 | |||
