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Signed-off-by: TsiChungLiew <[email protected]>
Signed-off by: John Rigby <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
Signed-off by: John Rigby <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
Signed-off by: John Rigby <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
Signed-off by: John Rigby <[email protected]>
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The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7
will cause the mpc8315erdb board can't boot up.
The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Now that all boards have been converted, remove old config code and the
config option for the new style.
Signed-off-by: Kumar Gala <[email protected]>
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Reworked the initial processor initialzation sequence:
* introduced cpu_early_init_f that is run in address space 1 (AS=1)
* Moved TLB/LAW and CCSR init into cpu_early_init_f()
* Reworked initial asm code to do most of the core init before TLBs
The main reasons for these changes are to allow handling of 36-bit phys
addresses in the future and some of the issues that will exist when we
do that.
There are a few caveats on what can be initialized via the LAW and TLB
static tables:
* TLB entry 14/15 can't be initialized via the TLB table
* any LAW that covers the implicit boot window (4G-8M to 4G) must map to
the code that is currently executing.
Signed-off-by: Kumar Gala <[email protected]>
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Add a set of functions to manipulate TLB entries:
* set_tlb() - write a tlb entry
* invalidate_tlb() - invalidate a tlb array
* disable_tlb() - disable a variable size tlb entry
* init_tlbs() - setup initial tlbs based on static table
Signed-off-by: Kumar Gala <[email protected]>
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All boards are now using the new fsl_law code so we can drop the old version.
Signed-off-by: Kumar Gala <[email protected]>
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Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.
Board code is responsible to provide a law_table and num_law_entries.
We should be able to use the same code on 86xx as well.
Signed-off-by: Kumar Gala <[email protected]>
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System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).
Signed-off by: Michael F. Reiss <[email protected]>
Signed-off by: Joe D'Abbraccio <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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The TSEC emergency priority definition of 831x/837x
is different than the definition of 834x in SPCR register.
Add the other config of TSEC emergency priority into
cpu_init.c
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Signed-off-by: Yoshihiro Shimoda <[email protected]>
CC: Nobuhiro Iwamatsu <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Oliver Weber <[email protected]>
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With recent toolchain versions, some boards would not build because
or errors like this one (here for ocotea board when building with
ELDK 4.2 beta):
ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab]
For many boards, the .bss section is big enough that it wraps around
at the end of the address space (0xFFFFFFFF), so the problem will not
be visible unless you use a 64 bit tool chain for development. On
some boards however, changes to the code size (due to different
optimizations) we bail out with section overlaps like above.
The fix is to add the NOLOAD attribute to the .bss and .sbss
sections, telling the linker that .bss does not consume any space in
the image.
Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Grzegorz Bernacki <[email protected]>
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Signed-off-by: Grzegorz Bernacki <[email protected]>
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Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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The DDR doesn't work on the 266MHz data rate,
the patch fix the bug.
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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New device trees will use "fsl,qe" compatible properties.
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Configure the number of bits used to address the banks inside the SDRAM
device. The default register value of 0 means 2 bits to address 4 banks.
Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks.
Signed-off-by: Becky Bruce <[email protected]>
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Signed-off-by: Larry Johnson <[email protected]>
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Change return values of init() functions in all Ethernet drivers to conform
to the following:
>=0: Success
<0: Failure
All drivers going forward should return 0 on success. Current drivers that
return 1 on success were left as-is to minimize changes.
Signed-off-by: Ben Warren <[email protected]>
Acked-by: Stefan Roese <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Acked-by: Kim Phillips <[email protected]>
Acked-by: Haavard Skinnemoen <[email protected]>
Acked-By: Timur Tabi <[email protected]>
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Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Define the layout of a binary blob that contains a QE firmware and instructions
on how to upload it. Add function qe_upload_firmware() to parse the blob and
perform the actual upload. Add command-line command "qe fw" to take a firmware
blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the
'firmware' device tree node if U-Boot has uploaded a firmware. Fully define
'struct rsp' in immap_qe.h to include the actual RISC Special Registers.
Signed-off-by: Timur Tabi <[email protected]>
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Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.
Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: Kumar Gala <[email protected]>
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The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Marcel Ziswiler <[email protected]>
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Signed-off-by: Marcel Ziswiler <[email protected]>
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This patch fixes several issues at least on a MPC885 based system with two
FEC interfaces used in MII mode.
1. PHY discovery should first read PHY_PHYIDR2 register and only then
PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it,
otherwise the values read are wrong. Also notice, that PHY discovery
cannot work on MPC88x / MPC87x in setups with both FECs active at all
in its present form, because for both interfaces the registers from FEC
1 are used to communicate over MII.
2. Remove code duplication for resetting the FEC by isolating it into a
separate function.
3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init().
4. Optimize mii_init() to only reset the FEC 1 controller once.
5. Fix a typo in mii_init() using index i instead of j thus potentially
leading to unpredictable results.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
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Conflicts:
board/tqm5200/tqm5200.c
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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The privious 4xx POST implementation only supported storing the POST
WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
we need to store the POST WORD in some other non volatile location.
This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
a location.
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well
Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.
Signed-off-by: Stefan Roese <[email protected]>
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This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.
Signed-off-by: Matthias Fuchs <[email protected]>
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