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Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs.
The AT91 ARM-based CPUs use basically the same hardware, so it should
be possible to share this driver, but no effort has been made so far.
Hardware documentation can be found in the AT32AP7000 data sheet,
which can be downloaded from
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Implement functions for configuring the mmci pins, as well as
functions for getting the clock rate of the mmci controller.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Implement functions for configuring the macb0 and macb1 pins, as
well as functions for getting the clock rate of the various
busses the macb ethernet controllers are connected to.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Relocate the u-boot image into SDRAM like everyone else does. This
means that we can handle much larger .data and .bss than we used to.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Rewrite the resource management code (i.e. I/O memory, clock gating,
gpio) so it doesn't depend on any global state. This is necessary
because this code is heavily used before relocation to RAM, so we
can't write to any global variables.
As an added bonus, this makes u-boot's memory footprint a bit smaller,
although some functionality has been left out; all clocks are enabled
all the time, and there's no checking for gpio line conflicts.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Split the avr32 initialization code into a function to run before
relocation, board_init_f and a function to run after relocation,
board_init_r. For now, board_init_f simply calls board_init_r
at the end.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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clear the Display after reset.
Signed-off-by: Heiko Schocher <[email protected]>
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There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
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This patch fixes changes the i2c_init(...) function to use the function
get_OPB_freq() rather than calculating the OPB speed by
sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is
specific per processor. The prior method was not and so was calculating
the wrong speed for some PPC4xx processors.
Signed-off-by: Jeffrey Mann <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Move the 8641HPCN's PIXIS code to the new directory
board/freescale/common/ as it will be shared by
future boards not in the same processor family.
Write a "pixis_reset" command that utilizes the FPGA
reset sequencer to support alternate soft-reset options
such as using the "alternate" flash bank, enabling
the watch dog, or choosing different CPU frequencies.
Add documentation for the pixis_reset to README.mpc8641hpcn.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
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...in preparation for improving the bootm command's handling of fdt blobs.
Also cleaned up some coding sloppiness.
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these definitions nor does any other arch include it
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Signed-off-by: Markus Klotzbuecher <[email protected]>
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Modifications to the existing code to support the new fdt command.
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Additional RAM information is now printed upon powerup, like
DDR2 frequency and CAS latency.
Signed-off-by: Stefan Roese <[email protected]>
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Fix a bug in the auto calibration routine. This driver now runs
more reliable with the tested modules. It's also tested with
167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Rodolfo Giometti <[email protected]>
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Reset support
BSP autoconfig support
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This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <[email protected]>
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This patch cleans up all the open issue of the preliminary
Acadia support.
Signed-off-by: Stefan Roese <[email protected]>
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Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
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Without this patch, I am unable to get to the prompt on rev 2 silicon.
Only set ddrioovcr for rev1.
Signed-off-by: Ed Swarthout<[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Markus Klotzbuecher <[email protected]>
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This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <[email protected]>
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for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <[email protected]>
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timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support
adding support for Xilinx ML401
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timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support
adding support for Xilinx ML401
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