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ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here
Add a warning in DDR1 case if cas_latency isn't a value we know about.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.
Signed-off-by: Victor Gallardo <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Adam Graham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).
Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B". DDR autocalibration Method_A scans the full range
of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B. Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.
The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1) SDRAM0_RQDC.[RQFD]
2) SDRAM0_RFDC.[RFFD]
This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:
1) SDRAM0_WRDTR.[WDTR]
2) SDRAM0_CLKTR.[CKTR]
3) SDRAM0_RQDC.[RQFD]
4) SDRAM0_RFDC.[RFFD]
and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].
Signed-off-by: Adam Graham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Cleans up some latent issues with the data cache control so that
dcache_enable() and dcache_disable() will work reliably (after
unlock_ram_in_cache() has been called)
Signed-off-by: Nick Spence <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Record the Arbiter Event Register values and optionally display them.
The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.
Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
#define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
and type register values
#define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter
event register values
Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
#define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
only events, so that it can still capture
other real problems.
Signed-off-by: Nick Spence <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.
lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.
Signed-off-by: Nick Spence <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.
Set gpio level register before direction register to inhibit
glitches on high level output pins.
Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.
Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.
Signed-off-by: Nick Spence <[email protected]>
Signed-off-by: Peter Korsgaard <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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Modified board_eth_init() functions of boards that have this FEC in addition
to other Ethernet controllers.
Affected boards:
bc3450
icecube
mvbc_p
o2dnt
pm520
total5200
tq5200
Removed initialization of controller from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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Added a cpu_eth_init() function to MPC512x CPU directory and
removed code from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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Removed at91sam9_eth_initialize() from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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This addresses all drivers whose initializers have already
been moved to board_eth_init()/cpu_eth_init().
Signed-off-by: Ben Warren <[email protected]>
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The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers. We create a default function that works
for most tsecs, and allow that to be overridden by board code. It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration. Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Ben Warren <[email protected]>
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The "GPIO" port mux is used on AVR32 UC3 parts as well as AT32AP7200 and
all later AVR32 chips. This patch adds a driver for it, implementing the
same API as the existing portmux-pio driver but with more functionality.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Replace the avr32-specific gclk_init() board hook with the standard
board_postclk_init() hook which is supposed to run at the same point
during initialization.
Provide a dummy weak alias for boards not implementing this hook. The
cost of this is:
- 2 bytes for the dummy function (retal 0)
- 2 bytes for each unnecessary function call (short rcall)
which is a pretty small price to pay for avoiding lots of #ifdef
clutter. In this particular case, all boards probably end up slightly
smaller because we avoid the conditional checking if the gclk_init
symbol is NULL.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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Add two helper functions for configuring and enabling generic clocks:
- gclk_enable_output: Enables output on a GCLKx pin
- gclk_set_rate: Configures a gclk to run at a specific rate
This should eliminate any reason to go mucking about with PM registers
from board code.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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- Separate the portmux configuration functionality from the GPIO pin
control API.
- Separate the controller-specific code from the chip-specific code.
- Allow "ganged" port configuration (multiple pins at once).
- Add more flexibility to the "canned" peripheral select functions:
- Allow using more than 23 address bits, more chip selects, as
well as NAND- and CF-specific pins.
- Make the MACB SPEED pin optional, and choose between MII/RMII
using a parameter instead of an #ifdef.
- Make it possible to use other MMC slots than slot 0, and support
different MMC/SDCard data bus widths.
- Use more reasonable pull-up defaults; floating pins may consume a
lot of power.
- Get rid of some custom portmux code from the mimc200 board code. The
old gpio/portmux API couldn't really handle its requirements, but
the new one can.
- Add documentation.
The end result is slightly smaller code for all boards. Which isn't
really the point, but at least it isn't any larger.
This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if
the board maintainers could help me test this on their boards. In
particular, the mimc200 port has lost a lot of code, so I'm hoping Mark
can help me out.
Signed-off-by: Haavard Skinnemoen <[email protected]>
Cc: Hans-Christian Egtvedt <[email protected]>
Cc: Mark Jackson <[email protected]>
Cc: Alex Raimondi <[email protected]>
Cc: Julien May <[email protected]>
Changes since v1:
* Enable pullup on NWAIT
* Add missing include to portmux-pio.h
* Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs
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Add support SH2/SH2A basic function.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could
try to enable the MMU, but map addresses 1-to-1, and disable data cache, then
it should work too and we could still profit from instruction cache.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
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Based on the original S3C64XX port by Samsung for U-Boot 1.1.6.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
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DM644x is just one of a series of DaVinci chips that use the EMAC driver.
By replacing all the function names that start with dm644x_* to davinci_*
we make these function more portable. I have tested this change on my EVM.
DM6467 is another DaVinci SOC which uses the EMAC driver and i will
be sending patches that add DaVinci DM6467 support to the list soon.
Signed-off-by: Sandeep Paulraj <[email protected]>
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This function is needed for the new NAND infrastructure. We only need
a dummy implementation though for the NDFC.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Ben Warren <[email protected]>
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Signed-off-by: Ben Warren <[email protected]>
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Made NAND bank configuration setting a config variable.
Signed-off-by: Wolfgang Ocker <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch fixes a UIC external_interrupt hang if critical or non-critical
interrupt is set at the same time as a normal interrupt is set on UIC0.
Signed-off-by: Victor Gallardo <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Removed Magic numbers from Initialization preload registers
Tested with Kilauea, Glacier, Canyonlands and Katmai boards
About 5-7% improvement seen for LMBench memtests
Signed-off-by: Prodyut Hazarika <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: TsiChung Liew <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.
Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.
Signed-off-by: Kumar Gala <[email protected]>
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The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We
also have SERDES init code for the 8536.
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Srikanth Srinivasan <[email protected]>
Signed-off-by: Dejan Minic <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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All 85xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Provide a helper function that board code can call to map TLBs when
setting up DDR.
Signed-off-by: Kumar Gala <[email protected]>
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Added a cpu_eth_init() function to leon2/leon3 CPU directories and
removed code from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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Added a cpu_eth_init() function to coldfire CPU directories and
removed code from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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Added a cpu_eth_init() function to cpu/mcf547x_8x directory and
removed code from net/eth.c
Signed-off-by: Ben Warren <[email protected]>
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All 86xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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