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Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor
on alchemy cpus.
Signed-off-by: Wolfgang Ocker <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
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Signed-off-by: Michal Simek <[email protected]>
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This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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-This patchs gives support for the embbedded ppc440
on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by Stefan Roese
Signed-off-by: Ricardo Ribalda Delgado <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors. Change the sense of detection so we
look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala <[email protected]>
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Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs. Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.
Signed-off-by: Paul Gortmaker <[email protected]>
Acked-by: Kim Phillips <[email protected]>
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With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB. The hardware silently truncates
them so the code happens to work. This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.
Signed-off-by: Andrew Klossner <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Kim Phillips <[email protected]>
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Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: Kim Phillips <[email protected]>
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ARM DaVinci: Remove extern phy_t declaration by moving
code to proper place.
Signed-off-by: Hugo Villeneuve <[email protected]>
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Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Signed-off-by: Marcel Ziswiler <[email protected]>
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caused by missing dcache status/enable/disable functions.
Signed-off-by: Hugo Villeneuve <[email protected]>
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This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Signed-off-by: Stefan Roese <[email protected]>
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Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If
CFG_CSn_RO is defined as 0, the chipselect will not
be assigned.
Signed-off-by: TsiChung Liew <[email protected]>
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Rename CONFIG_MCFTMR to CONFIG_MCFRTC to include real time
clock module in cpu/<cf arch>/cpu_init.c
Signed-off-by: TsiChung Liew <[email protected]>
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The compiling error was caused by missing a closed parentheses
in speed.c
Signed-off-by: TsiChung Liew <[email protected]>
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Signed-off-by: Kurt Mahan <[email protected]>
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Signed-off-by: Kurt Mahan <[email protected]>
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This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: Stefan Roese <[email protected]>
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This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Signed-off-by: Stefan Roese <[email protected]>
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This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.
Signed-off-by: Stefan Roese <[email protected]>
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This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: Grant Erickson <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).
With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).
Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:
PPC4xx IBM DDR2 Register Dump:
...
SDRAM_MB0CF[40] = 0x00006701
...
which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.
Tested on:
AMCC Kilauea/Haleakala:
- NFS Linux Boot: PASSED
- NAND Linux Boot: PASSED
Signed-off-by: Grant Erickson <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Feng Kan <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Kim Phillips <[email protected]>
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ADS5121 Rev 3 board is now the default config
config targets are now
ads5121_config
Rev 3 board with
PCI
M41T62 on board RTC
512MB DRAM
ads5121_rev2_config
Rev 2 board with
No PCI
256MB DRAM
Signed-off-by: Martha Marx <[email protected]>
Acked-by: Grant Likely <[email protected]>
Acked-by: John Rigby <[email protected]>
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Consolidate ADS5121 IO Pin configuration to one file
board/ads5121/iopin.c.
Remove pin config from cpu/mpc512x/fec.c
Signed-off-by: Martha Marx <[email protected]>
Acked-by: Grant Likely <[email protected]>
Acked-by: John Rigby <[email protected]>
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This patch fixes ppc4xx related printf format warning. Those warnings are
now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.
Signed-off-by: Stefan Roese <[email protected]>
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Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.
Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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