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With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Wolfgang Wallner <[email protected]>
Tested-by: Wolfgang Wallner <[email protected]>
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A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner <[email protected]>
Signed-off-by: Wolfgang Wallner <[email protected]>
Signed-off-by: Bernhard Messerklinger <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]> (Tested on coral)
Signed-off-by: Bin Meng <[email protected]>
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A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner <[email protected]>
Signed-off-by: Wolfgang Wallner <[email protected]>
Signed-off-by: Bernhard Messerklinger <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <[email protected]>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <[email protected]>
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