| Age | Commit message (Collapse) | Author |
|---|
|
Now that the patches have made it into mainline, we can also add the
commit IDs.
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
Added README file with the description of required options and host
configuration to use network SPL with am335x targets. Briefly discuss
how to use this configuration to program empty boards.
Signed-off-by: Ilya Yanok <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
|
|
Documentation fix to README.fsl-ddr to fix typos and
to reflect use of 'd' hotkey to enter the FSL DDR debugger.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.
Signed-off-by: James Yang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.
CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.
B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Sandeep Singh <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Signed-off-by: Troy Kisky <[email protected]>
|
|
Signed-off-by: Daniel Schwierzeck <[email protected]>
|
|
Signed-off-by: Daniel Schwierzeck <[email protected]>
|
|
|
|
|
|
Use a common watchdog driver for all these cpus.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Stefano Babic <[email protected]>
|
|
Add SPI device node data for exynos.
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Add sound device node data for exynos
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
|
|
|
|
The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.
This patch supports the following functions:
- 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Conflicts:
README
arch/arm/cpu/armv7/exynos/clock.c
board/samsung/universal_c210/universal.c
drivers/misc/Makefile
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/seaboard.h
|
|
Signed-off-by: Richard Genoud <[email protected]>
|
|
The silent variable now updates the global data flag anytime it is
changed as well as after the env relocation (in case its value is
different from the default env in such cases as NAND env)
Signed-off-by: Joe Hershberger <[email protected]>
|
|
Documentation of the GPT format.
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
|
|
Change e-mail address of Luka Perkov.
Signed-off-by: Luka Perkov <[email protected]>
CC: Luka Perkov <[email protected]>
|
|
This adds a docbook template for fs, and makes CBFS use it.
Signed-off-by: Simon Glass <[email protected]>
|
|
This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
[[email protected]: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <[email protected]>
|
|
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does. Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot. It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by: Scott Wood <[email protected]>
Cc: Andy Fleming <[email protected]>
|
|
|
|
Add LCD definitions and also a proposed binding for LCD displays.
The PWM is as per what will likely be committed to linux-next soon.
The displaymode binding comes from a proposal here:
http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html
The panel binding is new, and fills a need to specify the panel
timings and other tegra-specific information. Should a binding appear
that allows the pwm to handle this automatically, we can revisit
this.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
This binding will apparently soon be in linux-next. Bring it in now
since we need to do something, and may as well try to target what
Linux will have.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
|
|
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Matt Sealey <[email protected]>
Acked-by: Stefano Babic <[email protected]>
|
|
|
|
|
|
Grame is still listed since he has agreed to continue with some review.
Also add an alias to shorten things.
Signed-off-by: Simon Glass <[email protected]>
|
|
Based on previous work by: Alistair Buxton <[email protected]>
Signed-off-by: Pali Rohár <[email protected]>
Cc: Ивайло Димитров <[email protected]>
|
|
This makes the FAT and ext4 filesystem implementations build if
CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on
whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the
filesystems to be built separately from the filesystem-specific commands
that use them. This paves the way for the creation of filesystem-generic
commands that used the filesystems, without requiring the filesystem-
specific commands.
Minor documentation changes are made for this change.
The new config options are automatically selected by the old config
options to retain backwards-compatibility.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
|
|
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years. Get rid of the dead
weight.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
|
|
SX1 does not build properly by itself, is not built
as part of MAKEALL arm or MAKEALL -a arm, and is only
present in Makefile, not boards.cfg. As it also has no
entry in MAINTAINERS, it is orphan and non-functional.
Remove it.
Signed-off-by: Albert ARIBAUD <[email protected]>
|
|
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Add Freescale MCF54418TWR ColdFire development board support.
Signed-off-by: TsiChung Liew <[email protected]>
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Alison Wang <[email protected]>
|
|
|
|
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
SERDES Connections
32 lanes grouped into four 8-lane banks
Two “front side” banks dedicated to Ethernet
Two “back side” banks dedicated to other protocols
DDR Controllers
Three independant 64-bit DDR3 controllers
Supports rates up to 2133 MHz data-rate
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA
Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.
Detail information can be found in doc/README.t4qds
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.
Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Add code for configuring VSC3316/3308 crosspoint switches
Add README to understand the APIs
- VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch
capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16
output ports whereas VSC3308 has 8 input and 8 output ports.
Programming of these devices are performed by two-wire or four-wire
serial interface.
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
|
|
Implement kerneldoc template for linker-generated arrays. This is
the first template in U-Boot that is used to generate kerneldoc
style documentation. This template is very basic.
Signed-off-by: Marek Vasut <[email protected]>
|
|
This patch converts the old method of creating a list of command
onto the new LG-arrays code. The old u_boot_cmd section is converted
to new u_boot_list_cmd subsection and LG-array macros used as needed.
Minor adjustments had to be made to the common code to work with the
LG-array macros, mostly the fixup_cmdtable() calls are now passed the
ll_entry_start and ll_entry_count instead of linker-generated symbols.
The command.c had to be adjusted as well so it would use the newly
introduced LG-array API instead of directly using linker-generated
symbols.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
|
|
Conflicts:
drivers/serial/serial_lh7a40x.c
Signed-off-by: Tom Rini <[email protected]>
|
|
Add STDIO documentation template.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
[trini: Fix DOCBOOKS line as we don't have linker_lists yet]
Signed-off-by: Tom Rini <[email protected]>
|
|
Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.
Signed-off-by: Albert ARIBAUD <[email protected]>
|
|
Add entry for kerneldoc into the git-mailrc pointing to the U-Boot ML
and myself.
Signed-off-by: Marek Vasut <[email protected]>
|
