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path: root/drivers/clk/qcom/clock-qcs404.c
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2024-07-22drivers: clk: Remove duplicate newlinesMarek Vasut
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <[email protected]>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2024-05-07clk: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <[email protected]>
2024-04-04clk/qcom: use offsets for RCG registersCaleb Connolly
The RCG registers always have the same offsets, so only store the base CMD register address and calculate the others relative to that. Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-03-01clock/qcom: qcs404: fix clk_set_rateCaleb Connolly
We should be returning the rate that we set the clock to, drivers like MMC rely on this. So fix it. Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Sumit Garg <[email protected]> Tested-by: Sumit Garg <[email protected]> #qcs404 Signed-off-by: Caleb Connolly <[email protected]>
2024-01-16clk/qcom: fix rcg divider valueCaleb Connolly
The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro. However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors. Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms. Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-01-16clk/qcom: add mnd_width to clk_rcg_set_rate_mnd()Caleb Connolly
This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-01-16clk/qcom: use function pointers for enable and set_rateCaleb Connolly
Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined. Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]> [caleb: remove additional sysmap-sdm845.h mention]
2024-01-16clk/qcom: handle resets and clocks in one deviceKonrad Dybcio
Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>
2024-01-16clk/qcom: move from mach-snapdragonCaleb Connolly
Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <[email protected]> Signed-off-by: Caleb Connolly <[email protected]>