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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <[email protected]>
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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <[email protected]>
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.
Signed-off-by: Tom Rini <[email protected]>
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun <[email protected]>
CC: Simon Glass <[email protected]>
CC: Tom Rini <[email protected]>
CC: Heinrich Schuchardt <[email protected]>
CC: Thomas Schaefer <[email protected]>
CC: Masahiro Yamada <[email protected]>
CC: Robert P. J. Day <[email protected]>
CC: Alexander Merkle <[email protected]>
CC: Joakim Tjernlund <[email protected]>
CC: Curt Brune <[email protected]>
CC: Valentin Longchamp <[email protected]>
CC: Wolfgang Denk <[email protected]>
CC: Anatolij Gustschin <[email protected]>
CC: Ira W. Snyder <[email protected]>
CC: Marek Vasut <[email protected]>
CC: Kyle Moffett <[email protected]>
CC: Sebastien Carlier <[email protected]>
CC: Stefan Roese <[email protected]>
CC: Peter Tyser <[email protected]>
CC: Paul Gortmaker <[email protected]>
CC: Peter Tyser <[email protected]>
CC: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Variable "row_density" is no longer used. Drop it from DIMM structure.
Signed-off-by: York Sun <[email protected]>
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DDR controllers always use binding register to determine the memory
space to perform data initialization. In case of controller interleaving,
the space is doubled, resulting twice long wait. It wasn't too bad until
the memory capacity increases. To reduce the wait time, reduce the
binding space to half and restore it after data initialization.
Three-way interleaving is no longer used and is removed.
Signed-off-by: York Sun <[email protected]>
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DDR4 RDIMM has some information in SPD to be used to calculate the
control words for register chip. The rest can be found from JEDEC
spec DDR4RCD02.
Signed-off-by: York Sun <[email protected]>
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On top of RDIMM support, add new register calculation to support
3DS RDIMMs. Only symmetrical 3DS is supported at this time.
Signed-off-by: York Sun <[email protected]>
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Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.
Signed-off-by: York Sun <[email protected]>
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For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.
Signed-off-by: York Sun <[email protected]>
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This driver has been using printf() including filename since it was
added. Convert to using debug() instead.
Signed-off-by: Simon Goldschmidt <[email protected]>
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wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Signed-off-by: Raghav Dogra <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
[YS: Revised commit message]
Reviewed-by: York Sun <[email protected]>
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We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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Remove superfluous self assignements.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Assigning dev_num to itself is superfluous.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.
This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2t
This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.
Signed-off-by: Marek Behun <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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Fix compiling error of "no member named 'taamin_ps'" for DDR2.
Signed-off-by: York Sun <[email protected]>
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We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.
Signed-off-by: Simon Glass <[email protected]>
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The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <[email protected]>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <[email protected]>
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(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.
We should use && here.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.
Memory footprint will not increase as gcc will optimize out unused
constants.
Signed-off-by: Thomas Schaefer <[email protected]>
Signed-off-by: York Sun <[email protected]>
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Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
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This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <[email protected]>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <[email protected]>
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At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <[email protected]>
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Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <[email protected]>
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Use Kconfig to select errata workaround.
Signed-off-by: York Sun <[email protected]>
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Use Kconfig to select errata workaround.
Signed-off-by: York Sun <[email protected]>
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Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <[email protected]>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <[email protected]>
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- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <[email protected]>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <[email protected]>
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Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.
Signed-off-by: York Sun <[email protected]>
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Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.
Signed-off-by: York Sun <[email protected]>
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To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
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Fix various misspellings of:
* deprecated
* partition
* preceding,preceded
* preparation
* its versus it's
* export
* existing
* scenario
* redundant
* remaining
* value
* architecture
Signed-off-by: Robert P. J. Day <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c
Signed-off-by: Tom Rini <[email protected]>
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Instead of using multiple macros, a data structure is used to pass
board-specific parameters to MMDC DDR driver.
Signed-off-by: York Sun <[email protected]>
CC: Shengzhou Liu <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada <[email protected]>
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When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error
that temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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