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When using the fpga loads command, the driver is passing the AES encryption
key address is all cases. However, for the authenticated, but not encrypted
use case, there is no AES encryption key, and this value is 0.
When AES encryption is not used on the fpga bitstream, the pmufw assumes that
the AES key address is a bitstream size value like what is used by the
unsecure fpga load command.
To fix the problem, this patch checks to see if the AES key address is zero.
If the AES key address is zero, it means that AES is not being used on the
bitstream and the bitstream size should be passed instead. Thus, matching
the fpga load functionality.
Signed-off-by: Neal Frager <[email protected]>
Acked-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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There are missing Kconfig dependencies in the code which is using
firmware interface.
The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency")
add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig
dependencies were properly described and also sdhci and gem drivers
didn't protect the code properly.
So, add the missing ZYNQMP_FIRMWARE dependencies.
Signed-off-by: Algapally Santosh Sagar <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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There is no Kconfig option for this code, but it seems to be useful. Add
one.
Signed-off-by: Simon Glass <[email protected]>
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There is no Kconfig option for this code, but it seems to be useful. Add
one.
Signed-off-by: Simon Glass <[email protected]>
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At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This is always defined to 5, so use that as the default.
Cc: Michal Simek <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
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The fs_loader device is used to pull in settings via the chosen node.
However, there was no library function for this, so arria10 was doing it
explicitly. This function subsumes that, and uses ofnode_get_chosen_node
instead of navigating the device tree directly. Because fs_loader pulls
its config from the environment by default, it's fine to create a device
with nothing backing it at all. Doing this allows enabling
CONFIG_FS_LOADER without needing to modify the device tree.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_FPGA_CHECK_BUSY
Signed-off-by: Tom Rini <[email protected]>
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The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Warning appears if built with FPGA_DEBUG defined:
CC drivers/fpga/virtex2.o
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ssm_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:333:11: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
PRINTF("%s:%d:done went active early, bytecount = %d\n",
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
__func__, __LINE__, bytecount);
~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’
#define PRINTF(fmt, args...) printf(fmt, ##args)
^~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ss_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:468:12: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=]
PRINTF("%s:%d:done went active early, bytecount = %d\n",
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
__func__, __LINE__, bytecount);
~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’
#define PRINTF(fmt, args...) printf(fmt, ##args)
^~~
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The additional comma messes up the arguments.
Warning appears if built with FPGA_DEBUG defined:
CC drivers/fpga/spartan3.o
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:118:11: warning: too many arguments for format [-Wformat-extra-args]
PRINTF ("%s: Function Table:\n"
^~~~~~~~~~~~~~~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:18:37: note: in definition of macro ‘PRINTF’
#define PRINTF(fmt,args...) printf (fmt ,##args)
^~~
Fixes: 875c78934ee2 ("Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005")
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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That extra comma messes up format arguments.
Warning appears if built with FPGA_DEBUG defined:
CC drivers/fpga/spartan2.o
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c: In function ‘spartan2_sp_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:112:11: warning: too many arguments for format [-Wformat-extra-args]
PRINTF ("%s: Function Table:\n"
^~~~~~~~~~~~~~~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:12:37: note: in definition of macro ‘PRINTF’
#define PRINTF(fmt,args...) printf (fmt ,##args)
^~~
CC drivers/fpga/spartan3.o
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’:
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:117:11: warning: too many arguments for format [-Wformat-extra-args]
PRINTF ("%s: Function Table:\n"
^~~~~~~~~~~~~~~~~~~~~~~
/mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:17:37: note: in definition of macro ‘PRINTF’
#define PRINTF(fmt,args...) printf (fmt ,##args)
^~~
Fixes: e221174377d7 ("Initial revision")
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Those drivers could not be built anymore without those options present.
Signed-off-by: Alexander Dahl <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.
Suggested-by: Michal Simek <[email protected]>
Suggested-by: Simon Glass <[email protected]>
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.
Signed-off-by: Simon Glass <[email protected]>
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Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Tom Rini <[email protected]> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
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The drivers informs the user that a post config was not run after FPGA
configuration. This message is unnecessary in SPL because the
ps7_post_config function is called via spl_board_prepare_for_boot
function before jump_to_image_no_args function from board_init_r
function.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <[email protected]>
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Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to
handle loading encrypted bitfiles.
This feature requires encrypted FSBL, as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM
or eFUSEs, as a key source to the AES engine if the FSBL is not
encrypted. This prevents using the BBRAM or eFUSE as the key source
to the AES engine during run-time applications."
Signed-off-by: Adrian Fiergolski <[email protected]>
Co-developed-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to
handle loading authenticated images (DDR).
Based on solution by Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Check whether the FPGA ZynqMP driver supports the given bitstream
image type.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Reduce the function code by calling xilinx_pm_request() once only.
Use the same variable bsize_req to store either bstream size in bytes
or an address of bstream size according to a type required by the
firmware version. Remove obsolete debug().
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add a "compatible" string to binary flag converter, which uses
a callback str2flag() of given FPGA driver if available.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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This flag is used to check whether a Xilinx FPGA driver is able to
load a particular FPGA bitstream image.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add a call to convert FPGA "compatible" string to a binary flag.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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It allows using this feature without enabling the "fpga loads"
command.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Co-developed-by: Adrian Fiergolski <[email protected]>
Signed-off-by: Adrian Fiergolski <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK
Signed-off-by: Alexander Dahl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the
whitelist") downstream builds failed for boards setting this in
include/configs/…
Signed-off-by: Alexander Dahl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads the fat fs driver
doesn't have to allocate a temporary buffer in get_contents
(assuming 8KiB clusters).
* Change the buffer size to a larger value when reading to ddr
(but not too large, because large transfers cause a stack overflow
in the dwmmc driver).
Signed-off-by: Paweł Anikiel <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This converts the following to Kconfig:
CONFIG_FPGA_STRATIX_V
Signed-off-by: Tom Rini <[email protected]>
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Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Sin Hui Kho <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.04-rc3
qspi:
- Support for dual/quad mode
- Fix speed handling
clk:
- Add clock enable function for zynq/zynqmp/versal
gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path
fpga:
- Fix buffer alignment for ZynqMP
xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
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Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is
subtracted. It seems that the original intention was to just subtract
ARCH_DMA_MINALIGN. Fix it.
Signed-off-by: Michael Walle <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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At present this function does not accept a size for the FIT. This means
that it must be read from the FIT itself, introducing potential security
risk. Update the function to include a size parameter, which can be
invalid, in which case fit_check_format() calculates it.
For now no callers pass the size, but this can be updated later.
Also adjust the return value to an error code so that all the different
types of problems can be distinguished by the user.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Bruce Monroe <[email protected]>
Reported-by: Arie Haenel <[email protected]>
Reported-by: Julien Lenoir <[email protected]>
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Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang <[email protected]>
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Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.
Signed-off-by: Chee Hong Ang <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.
Signed-off-by: Chee Hong Ang <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
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