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We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3,
there are 4 i2c interface, but not 3. So the size of i2c_data array should
be calculated using "ARRAY_SIZE(i2c_bases)".
To avoid compile error, move i2c_bases before sram_data structure which
contains i2c_data array.
Signed-off-by: Peng Fan <[email protected]>
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This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2C
This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1
It has not been tested on Tegra 114 as I don't have that board.
Acked-by: Heiko Schocher <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.
Acked-by: Heiko Schocher <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
Acked-by: Heiko Schocher <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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"diconnect" and "disconnet" should both be "disconnect".
Signed-off-by: Mark Tomlinson <[email protected]>
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Due to an uninitialised variable, when muxes were deselected, any value
could be written to the mux control register. On the PCA9548, this could
result in multiple channels being selected, thus enabling multiple
pull-up resistors, and much bus capacitance.
The fix is simply to initialise the written value to zero.
Signed-off-by: Mark Tomlinson <[email protected]>
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U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Acked-by: Lukasz Majewski <[email protected]>
Tested-by: Lukasz Majewski <[email protected]>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Scott Jiang <[email protected]>
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Signed-off-by: Scott Jiang <[email protected]>
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Signed-off-by: Scott Jiang <[email protected]>
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In case of repeated START condition, the restart has to be kicked
before clear status (MSR register). If it is kicked after clear status,
R-Car I2C may transfer data (TXD register) or receive data (RXD register)
instead of transferring slave address (MAR register).
Signed-off-by: Ryo Kataoka <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Some slow I2C devices like Power Monitor(ZM7304) at times
do not work well with low timeout value, so I2C bus get stuck
during read cycle with this device, changing it to 100ms from
10ms works fine
A lot of other i2c drivers like mxc and i2c drivers of BOOTROM
also use relax timeouts to give sufficient ticks to work well
with slower devices
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
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ppc4xx i2c master gets stuck on errors while repeated start is
active. Can be easily reproduced by "i2c md" on an unpopulated
i2c address. There is not stop condition given, scl remains
pulled low.
The only way out seems to be doing a stop manually and then a
soft reset.
Signed-off-by: Dirk Eibach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Debugging some i2c trouble I saw on my scope that repeated
start is not working properply. The 4xx even held clock pulled down
after transfers. Having a look in the driver I realized
that IIC_CNTL_RPST is set on that part of the transfer that should
begin with a repeated start. But repeated start is about not sending a
stop condition, so IIC_CNTL_RPST has to be set on the last transfer
before the repeated start happens.
Signed-off-by: Dirk Eibach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Cc: Heiko Schocher <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
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In preparation for the SoCFPGA support of the designware I2C driver,
convert this driver to the common CONFIG_SYS_I2C framework.
This patch converts all users of this driver, this is:
- ST spearxxx boards
- AXS101 (ARC700 platform)
I couldn't test this patch on those boards. Only compile tested for all
spear boards. And tested on SoCFPGA.
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Acked-by: Alexey Brodkin <[email protected]>
Tested-by: Alexey Brodkin <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Vipin Kumar <[email protected]>
Cc: Jeroen Hofstee <[email protected]>
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Add support for I2C bus 1 on the i.MX28.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Heiko Schocher <[email protected]>
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This patch permeates the struct i2c_adapter throughout the driver,
so that it can be used to determine which adapter should be used.
Note that the driver still supports only one adapter. Note that
the patch does shuffle mxs_i2c_set_bus_speed() to the top of the
driver, but the function remains unchanged.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Heiko Schocher <[email protected]>
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This patch just converts the function prototypes used throughout
this driver to match those of the i2c framework. There is so far
no functional change. This patch does not do the deeper integration
of the framework bits.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Heiko Schocher <[email protected]>
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This patch prepares the MXS I2C driver for the conversion to the
new I2C driver framework by pulling out the hard-coded I2C0 address
from all the places.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Heiko Schocher <[email protected]>
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Include the i2c header and change the non confirming
functions to do so.
Cc: Heiko Schocher <[email protected]>
Signed-off-by: Jeroen Hofstee <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
[trini: Fix i2c_get_bus_num prototype]
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Jeroen Hofstee <[email protected]>
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To support the Armada XP SoC, we just need to include the correct header.
Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Tested-by: Luka Perkov <[email protected]>
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This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <[email protected]>
Tested-by: Luka Perkov <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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The macro MIN, MAX is defined as the aliase of min, max,
respectively.
Signed-off-by: Masahiro Yamada <[email protected]>
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This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
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The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang <[email protected]>
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Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
Acked-By: Prafulla Wadaskar <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
[ ijc -- updated u-boot-spl-fel.lds ]
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Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).
The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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Add support for 3rd and 4th I2C.
Signed-off-by: Shengzhou Liu <[email protected]>
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If a bus busy is detected when intializing the driver,
toggle 9 times the scl pin. Therefore enable the test mode
of the controller, in which the scl, sda pins can be
controlled manually.
Tested on the siemens boards pxm2, rut and dxr2.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Hannes Petermaier <[email protected]>
Cc: Lubomir Popov <[email protected]>
Cc: Steve Sakoman <[email protected]>
Cc: Sandeep Paulraj <[email protected]>
Cc: Vincent Stehlé <[email protected]>
Cc: Samuel Egli <[email protected]>
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Signed-off-by: Dirk Eibach <[email protected]>
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IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach <[email protected]>
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Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Varun Sethi <[email protected]>
Signed-off-by: Arnab Basu <[email protected]>
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Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.
Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Yen Lin <[email protected]>
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- "i2c mw" command hangs (with some compilers)
Signed-off-by: Steve Rae <[email protected]>
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These are used only once, so their is no need to have them global.
This also stops mvtwsi from using any bss vars making it easier to use
before dram init (to talk to the pmic to set the dram voltage).
Signed-off-by: Hans de Goede <[email protected]>
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The TWSI_FREQUENCY macro was wrong in 2 ways:
1) It was casting the result of the calculations to an u8, while i2c clk
rates are often >= 100Khz which won't fit in a u8, drop the cast.
2) It had an extra factor of 2 in the divider which neither the datasheet nor
the Linux driver have.
The comment for the default value was wrongly saying that m lives in
bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct
shift by 3 used in i2c_init().
While at it remove the unused twsi_actual_speed variable.
Signed-off-by: Hans de Goede <[email protected]>
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Conflicts:
drivers/net/Makefile
(trivial merge)
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Signed-off-by: Jesper B. Christensen <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.
Signed-off-by: Shaveta Leekha <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
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This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.
Signed-off-by: York Sun <[email protected]>
CC: Troy Kisky <[email protected]>
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- add davinci driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Vitaly Andrianov <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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