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Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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add nuvoton BMC npcm750 host configuration driver
Signed-off-by: Jim Liu <[email protected]>
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This converts the following to Kconfig:
CONFIG_SYS_FSL_SEC_MON
CONFIG_SYS_FSL_SEC_MON_BE
CONFIG_SYS_FSL_SEC_MON_LE
Signed-off-by: Tom Rini <[email protected]>
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Add Nuvoton BMC npcm750 otp driver
Signed-off-by: Jim Liu <[email protected]>
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Merge in v2022.07-rc5.
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This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.
The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.
The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.
I suggest using the following procedure for programming:
1. Override the fuses you wish to program
=> fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
=> fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
write-protect bit you will usually want to write it last anyway.
=> fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
=> fuse read 0 2 4
Signed-off-by: Sean Anderson <[email protected]>
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This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.
While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).
nvmem devices can specify "cells" in their device tree:
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00700000 0x100000>;
/* ... */
tsens_calibration: calib@404 {
reg = <0x404 0x10>;
};
};
which can then be referenced like:
tsens {
/* ... */
nvmem-cells = <&tsens_calibration>;
nvmem-cell-names = "calibration";
};
The tsens driver could then read the calibration value like:
struct nvmem_cell cal_cell;
u8 cal[16];
nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
nvmem_cell_read(&cal_cell, cal, sizeof(cal));
Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.
Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.
The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.
Signed-off-by: Sean Anderson <[email protected]>
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This patch adds a driver for configuration of the Microchip USB251xB/xBi
USB 2.0 hub controller series with USB 2.0 upstream connectivity, SMBus
configuration interface and two to four USB 2.0 downstream ports.
This is ported from Linux as of Linux kernel commit
5c2b9c61ae5d8 ("usb: usb251xb: add boost-up property support")
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Simon Glass <[email protected]>
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We have many cases of SPL (or TPL or VPL) drivers that don't depend on
SPL_MISC (and so on) but rather just MISC.
Cc: Sean Anderson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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We should only build support for misc if the appropriate SPL/TPL symbol
is defined. To ease the transition, make SPL/TPL_MISC default to MISC.
This is necessary because many drivers don't specify their dependencies
properly. These defaults can be removed once all drivers depend on the
appropriate config.
Fixes: aaba703fd0 ("spl: misc: Allow misc drivers in SPL and TPL")
Signed-off-by: Sean Anderson <[email protected]>
[trini: Add VPL_MISC symbol, handle like SPL/TPL_MISC]
Signed-off-by: Tom Rini <[email protected]>
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Add VPL versions of commonly used Kconfig options.
Signed-off-by: Simon Glass <[email protected]>
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ATSHA204A uses bit-reversed checksum of standard CRC-16 with polynomial
x^16 + x^15 + x^2 + 1.
This ATSHA204A specific checksum can be calculated just by using common
U-Boot functions bitrev16() and crc16().
So replace custom driver CRC-16 implementation by common U-Boot functions.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add a driver for the Gateworks System Controller used on Gateworks boards
which provides a boot watchdog, power control, temperature monitor,
and voltage ADCs.
Signed-off-by: Tim Harvey <[email protected]>
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Add a multi-function device driver which will probe its children and
provides methods to access the device.
Signed-off-by: Michael Walle <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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Enable fs_loader compilation at SPL Level.
Signed-off-by: Keerthy <[email protected]>
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
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This converts the following to Kconfig:
CONFIG_FSL_IFC
This is done via select statements to match previous logic.
Signed-off-by: Tom Rini <[email protected]>
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This is a "hex" prompt but the default value was given as an int.
Switch the default to hex (0x0) and remove the defconfigs that were
using the default, but as hex before.
Signed-off-by: Tom Rini <[email protected]>
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This allows removal of the OCOTP driver when SPL is enabled.
Disabling OCOTP reduces SPL size efficiently.
Signed-off-by: Michael Scott <[email protected]>
Co-developed-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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- Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDR
based on current usage.
- Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
to Kconfig. We move these symbols around a bit and add appropriate
dependencies to them. In some cases, we now add a correct default value
as well.
Signed-off-by: Tom Rini <[email protected]>
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UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ
selectable for all platforms.
Signed-off-by: Wasim Khan <[email protected]>
Tested-by: Vladimir Oltean <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add MMIO driver for QFW.
Note that there is no consumer as of this patch.
Signed-off-by: Asherah Connor <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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We move qfw into its own uclass and split the PIO functions into a
specific driver for that uclass. The PIO driver is selected in the
qemu-x86 board config (this covers x86 and x86_64).
include/qfw.h is cleaned up and documentation added.
Signed-off-by: Asherah Connor <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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At present several test drivers are part of the test file itself. Some of
these are useful for of-platdata tests. Separate them out so we can use
them for other things also.
A few adjustments are needed so this driver can build for sandbox_spl as
well.
Signed-off-by: Simon Glass <[email protected]>
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There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.
Signed-off-by: Michal Simek <[email protected]>
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In Intel's documentation the term P2SB stands for "Primary to Sideband
Bridge".
Signed-off-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]>
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Have this symbol follow the pattern of all other such symbols.
Signed-off-by: Trevor Woerner <[email protected]>
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The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.
Signed-off-by: Tero Kristo <[email protected]>
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The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.
Signed-off-by: Tero Kristo <[email protected]>
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Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.
Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Keerthy <[email protected]>
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The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.
Signed-off-by: Eugen Hristev <[email protected]>
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Signed-off-by: Peng Fan <[email protected]>
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Several options are presenting themselves on a various boards
where the options are clearly not used. (ie, SPL/TPL options
when SPL or TPL are not defined)
This patch is not attempting to be a complete list of items, but
more like low hanging fruit. In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.
This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: Adam Ford <[email protected]>
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In some cases it is necessary to read the keyboard in early phases of
U-Boot. The cros_ec keyboard is kept in the misc directory. Update the
config to allow this.
Signed-off-by: Simon Glass <[email protected]>
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While commit 3e020f03e94f ("driver: misc: add MXC_OCOTP Kconfig entry")
introduced a Kconfig entry it did not actually migrate all
configurations to using it.
As CONFIG_MXC_OCOTP was in mx{6/7}_common.h enable it by default on
those architectures. Additionally, also enable it on ARCH_IMX8M and
ARCH_VF610 where all current members enabled it through their legacy
configuration header files.
Signed-off-by: Marcel Ziswiler <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>
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All platforms are converted to DM_I2C that's why there is no reason to
keep this code here.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add driver for the efuse block in the JZ47xx SOC.
Cc: Daniel Schwierzeck <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which
supports initialization of the FPGA, as well as information gathering.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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This patch adds a driver for the bus associated with a IHS FPGA.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.
Signed-off-by: Liviu Dudau <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
Signed-off-by: Tien Fong Chee <[email protected]>
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Add a driver to configure the SerDes (Serializer/Deserializer) lanes on
the MPC83xx architecture.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
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This converts the following to Kconfig:
CONFIG_TWL4030_LED
CONFIG_TWL4030_INPUT
This also removes dead references to:
CONFIG_TWL4030_KEYPAD
Signed-off-by: Adam Ford <[email protected]>
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Add driver for the IHS IO endpoint on IHS FPGAs.
Signed-off-by: Mario Six <[email protected]>
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Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.
We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
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Add a driver for RXAUI control on IHS FPGAs.
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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