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For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need
to be set to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in i.MX53 reference manual:
29.7.8 Multi-block Read
For pre-defined multi-block read operation, that is,the number of blocks
to read has been defined by previous CMD23 for MMC, or pre-defined number
of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without
abort command at card side, an abort command, either automatic or manual
CMD12/CMD52, is still required by ESDHC after the pre-defined number of
blocks are done, to drive the internal state machine to idle mode. In this
case, the card may not respond to this extra abort command and ESDHC will
get Response Timeout. It is recommended to manually send an abort command
with RSPTYP[1:0] both bits cleared.
Signed-off-by: Jason Liu <[email protected]>
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Signed-off-by: John Rigby <[email protected]>
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Make existing field b_max field in struct mmc unconditional
and use it instead of CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_bread
and mmc_bwrite.
Initialize b_max to CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_register
if it has not been initialized by the hw driver.
Initialize b_max to 0 in all callers to mmc_register.
Signed-off-by: John Rigby <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Add support for the ARM PrimeCell MultiMedia Interface - PL180.
Ported from original device driver written by ST-Ericsson.
Signed-off-by: Matt Waddel <[email protected]>
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Hi Terry,
> So I guess:
> mmc_init calls mmc_send_op_cond that set high_capacity,
> than it calls mmc_startup, that, with MMC_CMD_SEND_CSD command, set
> the capacity, using values in CSD register.
> So I guess that mmc_change_freq should not recalculate high_capacity.
>
> It seems better, isn't it?
>
> Regards,
> Raffaele
>
Finally I think that it is enough to apply the following patch in order
to fix the issue.
Regards,
Raffaele
Signed-off-by: Andy Fleming <[email protected]>
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Defining CONFIG_MMC_TRACE in the include board file it is possible to activate
a tracing support.
This code helps in case of eMMC hw failure or to investigate possible eMMC
initialization issues.
Signed-off-by: Raffaele Recalcati <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The first SEND_OP_COND (CMD1) command added is used to ask card capabilities.
After it an AND operation is done between card capabilities and host
capabilities (at the moment only for the voltage field).
Finally the correct value is sent to the MMC, waiting that the card
exits from busy state.
Signed-off-by: Raffaele Recalcati <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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It is recommended to check card status after these kind of commands.
This is done using CMD13 (SEND_STATUS) JEDEC command until
the card is ready.
In case of error the card status field is displayed.
Signed-off-by: Raffaele Recalcati <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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This patch supports mmc/sd card with spi interface. It is based on
the generic mmc framework. It works with SDHC and supports multi
blocks read/write.
The crc checksum on data packet is enabled with the def,
There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time.
Signed-off-by: Thomas Chou <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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These local vars need not be writable nor exported.
Signed-off-by: Mike Frysinger <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error
would yield the first error return instead of TIMEOUT.
By swapping the test TIMEOUTs are reported as such
An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define
but as that one might be less desired I've opted for the simplest solution
Signed-off-by: Frans Meulenbroeks <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The maximum blocks value was hardcoded to 65535 due to a 16 bit
register length. The value can change for different platforms.
This patch makes the default the current value of 65535, but it
is configurable for other platforms.
Signed-off-by: Matt Waddel <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Fixed a bug wherein SD version 1.0 cards were not configured for 4-bit mode
Signed-off-by: Alagu Sankar <[email protected]>
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P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Don't forget to count full data size for the multiblock operation request.
Signed-off-by: Sonic Zhang <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.
Signed-off-by: Cliff Cai <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Signed-off-by: Mike Frysinger <[email protected]>
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Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.
It is now calculated based upon the request sent by mmc subsystem.
Signed-off-by: Chander Kashyap <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Acked-by: Mingkai Hu <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Added support for MMC/SD cards for Davinci. This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.
Signed-off-by: Alagu Sankar <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: Jerry Huang <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao <[email protected]>
Signed-off-by: Li Yang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.
Signed-off-by: Li Yang <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The max clock of MMC is 52MHz
Signed-off-by: Jerry Huang <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.
Signed-off-by: P.V.Suresh <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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Signed-off-by: Reinhard Meyer <[email protected]>
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Having a loop with a counter is no timing guarentee for timing
accuracy or compiler optimizations. For e.g. the same loop counter
which runs when the MPU is running at 600MHz will timeout in around
half the time when running at 1GHz. or the example where GCC 4.5
compiles with different optimization compared to GCC 4.4. use timer
to keep track of time elapse and we use an emperical number - 1sec
for a worst case timeout. This should never happen, and is adequate
imaginary condition for us to fail with timeout.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <[email protected]>
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This patch adds multi-block read support for the generic MMC
driver. Large reads are broken into chunks of 65535 blocks to
ensure that the code works with controllers having a 16 bit block counter.
This patch results in a significant performance improvement.
Time to read a 45 MB file went from 36 seconds to 9 seconds on Overo
Signed-off-by: Steve Sakoman <[email protected]>
Tested-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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The current mmc write implementation is type ulong, but returns int values.
Some of the printf's are terminated with /n/r, one has none.
This patch fixes these issues and also removes some unnecessary local
variables.
Signed-off-by: Steve Sakoman <[email protected]>
Signed-off-by: Sandeep Paulraj <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Constraint the mmc framework to only send no more than 65535
blocks in one go during the multi-write command. This constraint
comes due to the limitation of 16bit width block counter register
at some hardware.
Signed-off-by: Lei Wen <[email protected]>
Cc: Reinhard Meyer <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
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This Patch do support 8-bit bus width for s5p
So we add parameter for bus_width (in s5p_mmc_init(), s5p_mmc_initialize())
If want to use 8-bit bus width, only change (0, 8) instead of (0, 4).
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
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OMAP boards currently use a legacy mmc driver. This patch adds a new
mmc driver which will work with the generic mmc driver in u-boot.
This new driver will work with both OMAP3 and OMAP4 boards.
This patch does not remove the old driver. It should remain in the
tree until all boards that use it switch to the new driver.
Signed-off-by: Sukumar Ghorai <[email protected]>
Tested-by: Steve Sakoman <[email protected]>
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The current mmc driver returns erroneous capacity information for
eMMC. The capacity of eMMC devices is available only in the ext-CSD
register. This patch add code to read the ext-CDSD register and
correctly calculate eMMC capacity.
Signed-off-by: Sukumar Ghorai <[email protected]>
Acked-by: Steve Sakoman <[email protected]>
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Simplify the command setup and status checking steps, and add a proper
timeout to the status polling code to avoid possible infinite hangs.
Signed-off-by: Mike Frysinger <[email protected]>
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Commit d2bf29e3 caused a number of compiler warnings:
mmc.c: In function 'mmc_bwrite':
mmc.c:97: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'long unsigned int'
mmc.c:97: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'lbaint_t'
mmc.c: In function 'mmc_bread':
mmc.c:229: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'long unsigned int'
mmc.c:229: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'lbaint_t'
Fix these.
Signed-off-by: Wolfgang Denk <[email protected]>
Cc: Lei Wen <[email protected]>
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Signed-off-by: Lei Wen <[email protected]>
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Signed-off-by: Reinhard Meyer <[email protected]>
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base address
This patch is intended to prepare the other S5P SoC. (s5pc210)
If use SoC specific defines then can't share with other SoC.
So, make the accessor functions for access the base address by common way.
Signed-off-by: Minkyu Kang <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
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