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This patch adds MMC_HS_52 to the timing data structure.
Previously, this bus mode tap settings were not populated and
were instead populated for MMC_HS which is a different bus mode
up to 26MHz. Since we intended these settings according to the
device data sheet[0] for MMC_HS_52 up to 52MHz, populate MMC_HS
tap settings for MMC_HS_52.
While we are here, fix typo in ti,itap-del-sel-mms-hs.
[0] https://www.ti.com/lit/ds/symlink/am625.pdf Table 7-79
Signed-off-by: Judith Mendez <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/25909
Please pull the updates for rockchip platform:
- New SoC support: RK3528, RK3576
- New Board support: rk3528 Radxa E20C, rk3576 Firefly ROC-RK3576-PC;
- Add generic board for rk3288 and rk3399;
- rng driver binding update;
- misc updates on board level or header files;
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The rk3576 uses a different base-compatible, as starting with this
generation, the clock phase tuning is done via registers inside
the mmc controller and not from inside the CRU.
In U-Boot we do not tune at all, so no other code changes are
necessary.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for RK3576 to the rockchip sdhci driver.
It's pretty similar to its cousins found in the RK3568 and RK3588 and the
specific hs400-tx-tap number was taken from the vendor-u-boot.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency
TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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This callback is used to send the 74 clock cycles after power up.
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add a new callback function *send_init_stream* which start a sequence of
at least 74 clock cycles.
The mmc core uses *mmc_send_init_stream* in order to invoke the callback
function. This will be used during power cycle where the specification
requires such a sequence after power up.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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%s/Relatvie/Relative'
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Airoha new SoC implement the same Mediatek driver for MMC. Permit to
also build for Airoha arch.
Signed-off-by: Christian Marangi <[email protected]>
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Tom Rini <[email protected]> says:
This series switches to always using $(PHASE_) in Makefiles when
building rather than $(PHASE_) or $(XPL_). It also starts on documenting
this part of the build, but as a follow-up we need to rename
doc/develop/spl.rst and expand on explaining things a bit.
Link: https://lore.kernel.org/r/[email protected]
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It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.
Signed-off-by: Tom Rini <[email protected]>
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resizing
Current mmc bootpart-resize command only support Samsung eMMC BOOT/RPMB
hardware partition resizing. Add Sandisk and Micron eMMC BOOT/RPMB hardware
partition resizing support. The commands and parameters for resizing
partitions are different for each manufacturer. Select the corresponding
function according to CID.
Signed-off-by: Luke Wang <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Each MMC device has a child which ihs a block device. At present we call
mmc_deinit() when the block device is removed.
But the MMC struct (i.e. struct mmc) is attached to the MMC's device,
not its child.
So at present, when an MMC device is removed, mmc_deinit() is called
twice, once for the MMC device and once for its block device. This
results in a double call to cyclic_unregister().
Fix this by adding a 'remove' method to the uclass and calling
mmc_deinit() from there.
Also drop the call to device_probe() within the block-device's probe()
method. The device is already in the process of being probed, so this
call does nothing.
Signed-off-by: Simon Glass <[email protected]>
Fixes: c822c1a50bd ("mmc: call device_probe() after scanning")
Signed-off-by: Peng Fan <[email protected]>
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When MMC_SDHCI_SDMA=y or MMC_SDHCI_ADMA=y and PIO mode is used
dma_unmap_single() is called on an unmapped address, 0x0. This may
result in a Synchronous Abort:
## Checking hash(es) for Image atf-1 ... sha256+ OK
CMD_SEND:16
ARG 0x00000200
MMC_RSP_R1,5,6,7 0x00000900
CMD_SEND:18
ARG 0x00004005
"Synchronous Abort" handler, esr 0x96000147
elr: 00000000400015bc lr : 0000000040012b4c
x 0: 0000000000008000 x 1: 0000000000092600
x 2: 0000000000000040 x 3: 000000000000003f
x 4: 0000000000000030 x 5: 0000000000000001
x 6: 0000000000000001 x 7: 0000000000000000
x 8: 000000000000000a x 9: 0000000000000090
x10: 0000000043dffc68 x11: 0000000043c00440
x12: 0000000043c00440 x13: ffffffffbfe00000
x14: 000000000000031c x15: 0000000240000000
x16: 000000004001145c x17: 0000000000000032
x18: 0000000043dffef0 x19: 0000000043c00000
x20: 0000000043dffbc8 x21: 0000000000000000
x22: 00000000000f3d95 x23: 0000000000000002
x24: 0000000000000493 x25: 0000000000092600
x26: 0000000000000001 x27: 0000000000000001
x28: 0000000000000008 x29: 0000000043dffab0
Code: d2800082 9ac32042 d1000443 8a230000 (d5087620)
Resetting CPU ...
resetting ...
Fix this by only dma_unmap_single() when DMA mode is used and
sdhci_prepare_dma() has been called to map host->start_addr.
Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Per JESD84-B51 6.6.9 Erase:
The host can erase a contiguous range of Erase Groups. Starting the erase
process is a three steps sequence. First the host defines the start address
of the range using the ERASE_GROUP_START (CMD35) command, next it defines
the last address of the range using the ERASE_GROUP_END (CMD36) command and
finally it starts the erase process by issuing the ERASE (CMD38) command
with argument bits set to zero. See Table 11 for the arguments supported by
CMD38. The address field in the erase commands is an Erase Group address,
in byte units for densities up to 2GB, and in sector units for densities
greater than 2GB. The Device will ignore all LSB's below the Erase Group
size, effectively rounding the address down to the Erase Group boundary.
So choose 2GB bytes as check condition.
If the erase size is larger that 2GB, use 2GB to avoid breaking non high
capacity cards. If erase size is less than 2GB and larger than a grp, use
'grpcnt * mmc->erase_grp_size' to cover all the sectors, else use
the number of sectors.
With test erasing 20GB eMMC
board: Evk_8ulp Evk_8mm Evk_8mn Evk_8mp Mek_8qxpc0 Mek_8qm
kingston sandisk
before: 37.683s 112.738s 129.365s 28.238s 112.605s 500.470s 490.708s
after: 0.093s 0.111s 0.951s 0.080s 0.121s 6.960s 6.915s
Tested-by: Faqiang Zhu <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In case mmc_complete_init() returns error, exit from mmc_init()
without possibly calling cyclic_register(), which at that point
would be undesired.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Simplify 90cc07fd786d ("mmc: Poll CD in case cyclic framework is enabled")
according to suggestions by Rasmus. The struct cyclic_info is zero-size in
case CONFIG_CYCLIC is not enabled and does not add any size to struct mmc,
so it can unconditionally be part of that structure. This allows clean up
of all the other conditionals in mmc.c which can now be unconditionally
present, as they also add no extra space.
Suggested-by: Rasmus Villemoes <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The option MMC_SDHCI_ADMA_FORCE_32BIT is only tested or used when
MMC_SDHCI_ADMA or SPL_MMC_SDHCI_ADMA is enabled. And for
MMC_SDHCI_ADMA_64BIT the same is true except we also require
MMC_SDHCI_ADMA_FORCE_32BIT to be disabled.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Acked-by: Peng Fan <[email protected]>
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Cards should always be reset and threshold set. This fixes eMMC on H616.
Signed-off-by: Jernej Skrabec <[email protected]>
[Andre: use macro-defined offsets to fix build on older SoCs]
Signed-off-by: Andre Przywara <[email protected]>
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On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
But we have still the hidden divisor of 2 in the MMC mod clock, so
need to explicitly compensate for that on those SoCs.
This leads to the actually programmed clock rate to be double compared
to before, which increases the MMC performance on those SoCs.
Signed-off-by: Andre Przywara <[email protected]>
Reported-by: Kuba Szczodrzyński <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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U-Boot has to reconfigure the clocks that were set in the boot
loaders. However, in IPQ9574, the clocks have to be reset before
they can be reconfigured. Hence add code to do the relevant
resets.
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Caleb Connolly <[email protected]>
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The flag for enabling the ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE quirk can be
handled easily enough in Kconfig. This lets us remove a function but not
obviously correct usage of the IS_ENABLED() macro.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Co-developed-by: Greg Malysa <[email protected]>
Signed-off-by: Greg Malysa <[email protected]>
Co-developed-by: Ian Roberts <[email protected]>
Signed-off-by: Ian Roberts <[email protected]>
Signed-off-by: Vasileios Bimpikas <[email protected]>
Signed-off-by: Utsav Agarwal <[email protected]>
Signed-off-by: Arturs Artamonovs <[email protected]>
Signed-off-by: Oliver Gaskell <[email protected]>
Signed-off-by: Nathan Barrett-Morrison <[email protected]>
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For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51
section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT
should not be used to determine device size, and instead device size
should be calculated from C_SIZE and C_SIZE_MULT.
This is not exactly accurate, the 2 GiB limit is not a hard line,
there are eMMC devices which are smaller than 2 GiB and still
require device size to be determined from EXT_CSD SEC_COUNT. The
hard line is instead OCR HCS bit, which indicates whether the device
is byte or sector addressed, the former applies to most devices
below 2 GiB, and the later applies mostly to devices above 2 GiB.
However, there are a couple of devices which are smaller than 2 GiB
and still set the OCR HCS bit to indicate they are sector addressed,
and therefore the size calculation for those devices should also
use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the
devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag
reflects the OCR HCS bit state.
Fixes: 639b7827d1ca ("mmc: fix the condition for MMC version 4")
Signed-off-by: Marek Vasut <[email protected]>
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VPL may want to use driver model for MMC even if TPL does not. Update
the rule in this driver to support that.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This patch adds eMMC/SD support for MT7987 SoC
Signed-off-by: Weijie Gao <[email protected]>
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The BLK symbol has a few meanings, one of which is that it controls the
driver model portion of a "block device". Rather than having this hidden
symbol be "default y if ..." it should be select'd by the various block
subsystems. Symbols such as PVBLOCK which already select'd BLK are
unchanged".
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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At this point in time, DM is always enabled. So if MMC is enabled, it
should select DM_MMC. No drivers need to depend on DM_MMC being enabled
now, so remove that from dependency lists. This now means that a number
of platforms which select'd DM_MMC need to select MMC instead. This also
fixes a migration problem with espresso7420 in that MMC is built again
with the platform.
Reviewed-by: Peter Robinson <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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At this point in time, we know that with the MMC symbol enabled we will
always also have the BLK symbol enabled, so we do not need to list that
as a dependency for MMC drivers.
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Prepare v2025.01-rc5
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Add support for DesignWare SDHCI host controller on Alibaba TH1520 SoC
Signed-off-by: Maksim Kiselev <[email protected]>
Tested-by: Heinrich Schuchardt <[email protected]>
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Make the U-Boot JH7110 MMC driver compatible with upstream DT.
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
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On 64bit systems the timer value might be truncated to a 32bit value
causing malfunctions. For example on ARM the timer might start from 0
again only after a cold reset. The 32bit overflow occurs after a bit
more than 49 days (1000 Hz counter) so booting after that time may lead
to a surprise because the board might become stuck requiring a cold
reset.
Signed-off-by: Ronald Wahl <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The correct spelling is R-Car, including the dash, update the usage.
Comment changes only, no functional change.
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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On earlier platforms, the vqmmc regulator was enabled by the
previous bootloader, but on the newest (SM8650) it's not
and we need vqmmc to be enabled in order to have the card
to respond.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
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After the recent dts/upstream subtree merge, the sdhi compatible string
used in the device tree for RZ/G2L family SoCs is "renesas,rzg2l-sdhi"
not "renesas,rcar-gen3-sdhi". This broke the ability to access the eMMC
and SD card devices on RZ/G2L boards.
Fix this by adding the new compatible string to the sdhi driver.
Fixes: 136b7b6d2e98 ("Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream")
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Paul Barker <[email protected]>
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Convert to using livetree API functions.
Without this if livetree is enabled (OF_LIVE) the fsl_esdhc_imx
driver will fail to read vendor-specific properties from the dt.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The commit 0252924ac6d4 ("mmc: dw_mmc: Extract FIFO data transfer into a
separate routine") unintentionally changed behavior of the FIFO data
transfer routine.
When data is read and size reaches 0 the original loop would wait on
DWMCI_INTMSK_DTO or timeout. The remaining size to read and buf position
is no longer tracked across dwmci_data_transfer_fifo() calls and because
of this an extra call to fifo() and dwmci_fifo_ready() may now trigger a
FIFO underflow timeout error and slows down FIFO reading.
Buswidth = 4, clock: 50000000
Sending CMD16
Sending CMD17
dwmci_fifo_ready: FIFO underflow timeout
Sending CMD16
Sending CMD18
dwmci_fifo_ready: FIFO underflow timeout
Sending CMD12
## Checking hash(es) for config config-1 ... OK
This reverts commit 0252924ac6d4af69061bb9589d16b30c5bdb7178 to restore
the old working behavior.
Fixes: 0252924ac6d4 ("mmc: dw_mmc: Extract FIFO data transfer into a separate routine")
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Quentin Schulz <[email protected]> # RK3588 Tiger
Reviewed-by: Simon Glass <[email protected]>
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Raymond Mao <[email protected]> says:
Integrate MbedTLS v3.6 LTS (currently v3.6.0) with U-Boot.
Motivations:
------------
1. MbedTLS is well maintained with LTS versions.
2. LWIP is integrated with MbedTLS and easily to enable HTTPS.
3. MbedTLS recently switched license back to GPLv2.
Prerequisite:
-------------
This patch series requires mbedtls git repo to be added as a
subtree to the main U-Boot repo via:
$ git subtree add --prefix lib/mbedtls/external/mbedtls \
https://github.com/Mbed-TLS/mbedtls.git \
v3.6.0 --squash
Moreover, due to the Windows-style files from mbedtls git repo,
we need to convert the CRLF endings to LF and do a commit manually:
$ git add --renormalize .
$ git commit
New Kconfig options:
--------------------
`MBEDTLS_LIB` is for MbedTLS general switch.
`MBEDTLS_LIB_CRYPTO` is for replacing original digest and crypto libs with
MbedTLS.
`MBEDTLS_LIB_CRYPTO_ALT` is for using original U-Boot crypto libs as
MbedTLS crypto alternatives.
`MBEDTLS_LIB_X509` is for replacing original X509, PKCS7, MSCode, ASN1,
and Pubkey parser with MbedTLS.
By default `MBEDTLS_LIB_CRYPTO_ALT` and `MBEDTLS_LIB_X509` are selected
when `MBEDTLS_LIB` is enabled.
`LEGACY_CRYPTO` is introduced as a main switch for legacy crypto library.
`LEGACY_CRYPTO_BASIC` is for the basic crypto functionalities and
`LEGACY_CRYPTO_CERT` is for the certificate related functionalities.
For each of the algorithm, a pair of `<alg>_LEGACY` and `<alg>_MBEDTLS`
Kconfig options are introduced. Meanwhile, `SPL_` Kconfig options are
introduced.
In this patch set, MBEDTLS_LIB, MBEDTLS_LIB_CRYPTO and MBEDTLS_LIB_X509
are by default enabled in qemu_arm64_defconfig and sandbox_defconfig
for testing purpose.
Patches for external MbedTLS project:
-------------------------------------
Since U-Boot uses Microsoft Authentication Code to verify PE/COFFs
executables which is not supported by MbedTLS at the moment,
addtional patches for MbedTLS are created to adapt with the EFI loader:
1. Decoding of Microsoft Authentication Code.
2. Decoding of PKCS#9 Authenticate Attributes.
3. Extending MbedTLS PKCS#7 lib to support multiple signer's certificates.
4. MbedTLS native test suites for PKCS#7 signer's info.
All above 4 patches (tagged with `mbedtls/external`) are submitted to
MbedTLS project and being reviewed, eventually they should be part of
MbedTLS LTS release.
But before that, please merge them into U-Boot, otherwise the building
will be broken when MBEDTLS_LIB_X509 is enabled.
See below PR link for the reference:
https://github.com/Mbed-TLS/mbedtls/pull/9001
Miscellaneous:
--------------
Optimized MbedTLS library size by tailoring the config file
and disabling all unnecessary features for EFI loader.
From v2, original libs (rsa, asn1_decoder, rsa_helper, md5, sha1, sha256,
sha512) are completely replaced when MbedTLS is enabled.
From v3, the size-growth is slightly reduced by refactoring Hash functions.
From v6, smaller implementations for SHA256 and SHA512 are enabled and
target size reduce significantly.
Target(QEMU arm64) size-growth when enabling MbedTLS:
v1: 6.03%
v2: 4.66%
v3 - v5: 4.55%
v6: 2.90%
Tests done:
-----------
EFI Secure Boot test (EFI variables loading and verifying, EFI signed image
verifying and booting) via U-Boot console.
EFI Secure Boot and Capsule sandbox test passed.
Known issues:
-------------
None.
Link: https://lore.kernel.org/u-boot/[email protected]/
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Adapt digest header files to support both original libs and MbedTLS
by switching on/off MBEDTLS_LIB_CRYPTO.
Introduce <alg>_LEGACY kconfig for legacy hash implementations.
sha256.o should depend on SHA256 kconfig only but not SUPPORT_EMMC_RPMB,
SHA256 should be selected when SUPPORT_EMMC_RPMB is enabled instead.
`IS_ENABLED` or `CONFIG_IS_ENABLED` is not applicable here, since
including <linux/kconfig.h> causes undefined reference on schedule()
with sandbox build, as <linux/kconfig.h> includes <generated/autoconf.h>
which enables `CONFIG_HW_WATCHDOG` and `CONFIG_WATCHDOG` but no schedule()
are defined in sandbox build,
Thus we use `#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)` instead.
Signed-off-by: Raymond Mao <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Simon Glass <[email protected]> says:
When the SPL build-phase was first created it was designed to solve a
particular problem (the need to init SDRAM so that U-Boot proper could
be loaded). It has since expanded to become an important part of U-Boot,
with three phases now present: TPL, VPL and SPL
Due to this history, the term 'SPL' is used to mean both a particular
phase (the one before U-Boot proper) and all the non-proper phases.
This has become confusing.
For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL'
phases, not just SPL. So code which can only be compiled for actual SPL,
for example, must use something like this:
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
In Makefiles we have similar issues. SPL_ has been used as a variable
which expands to either SPL_ or nothing, to chose between options like
CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable
was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was
updated to support 'VPL_' as well.
This series starts a change in terminology and usage to resolve the
above issues:
- The word 'xPL' is used instead of 'SPL' to mean a non-proper build
- A new CONFIG_XPL_BUILD define indicates that the current build is an
'xPL' build
- The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now
defined for TPL and VPL phases
- The existing SPL_ Makefile variable is renamed to SPL_
- The existing SPL_TPL Makefile variable is renamed to PHASE_
It should be noted that xpl_phase() can generally be used instead of
the above CONFIGs without a code-space or run-time penalty.
This series does not attempt to convert all of U-Boot to use this new
terminology but it makes a start. In particular, renaming spl.h and
common/spl seems like a bridge too far at this point.
The series is fully bisectable. It has also been checked to ensure there
are no code-size changes on any commit.
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Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.
Update the comment in bootstage to refer to this symbol, instead of
SPL_
Signed-off-by: Simon Glass <[email protected]>
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Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.
Signed-off-by: Simon Glass <[email protected]>
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Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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When supporting partition reset for SoC such as i.MX95 , the Linux
Kernel may have configured the tuning, while after force reset by
wdog or else, uboot CMD0 will never pass unless config RSTT to reset
tuning logic.
Since RSTA and RSTT are independent, so need both to be reseted in the
controller.
Acked-by: Haibo Chen <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The memory of priv and plat are leaked if max_bus_width is wrong.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The plat->cfg is wrongly memset to 0, so the host_caps value configured
in fsl_esdhc_initialize is reset. Remove the unnecessary memset since
plat is allocated via calloc.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to SD and MMC spec, 74 clocks must be sent to device after
power stable. This is need in reinit ops for DM MMC or init ops for
non-DM MMC after power cycle.
So set the INTIA to send 80 clocks in esdhc_init_common and move
its calling from probe to reinit.
However, on 8MQ EVK and 8QXP MEK with some brands of SD cards, sending
80 clocks may not work well.
The root cause is related with power up time. According to spec, after
power stable, host shall supply at least 74 SD clocks to the SD card with
the maximum of 1ms. However, the power ram up time is related with the
characteristic of SD card. At the moment of sending 74 SD clocks, the
power probably not ram up to the operating level on the problematic
cards. Then cause the cards not ready.
This patch changes to send SD clock with 1ms duration to replace 80
SD clocks (0.2ms at 400Khz clock).
This way meets the spec requirement as well, and adds the margin for
power ram up time to be compatible with the problematic SD cards.
This is also aligned with implementation which has FORCE clock
always on.
Reviewed-and-tested-by: Haibo Chen <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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