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Allwinner R329 has no MMC2.
Only include the code of MMC2 if the base address of it is defined.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Mini emmc does not use any pmufw and ZYNQMP_FIRMWARE is disabled.
xilinx_pm_request() will not be compiled and causes undefined reference to
`xilinx_pm_request' error. So add a weak function in zynq_sdhci.c file.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20211020
-------------------
First PR from u-boot-imx for 2022.01
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535
- new board: kontron-sl-mx8mm
- imx8m:
- fix secure boot
- imx ESDHC: fixes
- i.MX53: Support thum2, bmode and fixes for Menlo board
usbarmory switch to Ethernet driver model
- imx6 :
- DDR calibration for Toradex boards
- imx7:
- Fixes
- Updated gateworks boards (ventana / venice)
# gpg verification failed.
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The default configuration of rk3399 EMMC PHY does not enable the
strobe line, and EMMC controller will got data transmission error
at HS400 mode.
Signed-off-by: Yifeng Zhao <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will
remove the asm/arch/gpio.h header. In preparation, clean up the various
files that include it.
Some files did not contain any GPIO code at all, so this header was
completely unused.
A few files contained only legacy platform-specific GPIO code for
setting up pin muxes. They were left unchanged, as that code will be
completely removed by the DM_PINCTRL migration.
The remaining files contain some combination of DM_GPIO and legacy GPIO
code. For those, switch to including asm/gpio.h (if it wasn't included
already). Right now, this header provides both sets of functions,
because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the
right header to include once the DM_GPIO migration is complete and
GPIO_EXTRA_HEADER is no longer needed.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
for slave sel value. If this register bits value is 0, it needs
256 ref_clk cycles to update slave sel value. IC suggest to set
bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
sel value. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change
to add 5us delay.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel.
Set supported by u-boot flags only.
Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
Signed-off-by: Ricardo Salveti <[email protected]>
Co-developed-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Oleksandr Suvorov <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it
only works when UHS is enabled. However, in SD initialization the
power cycle does not depends on UHS. But the power cycle needs
disable the SD clock before power down.
So this causes a problem when UHS is not enabled. Some cards can't
become ready (ACMD14 timeout) due to the clock is enabled during
power cycle.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Haibo Chen <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This board has not been converted to CONFIG_DM by the deadline.
Remove it. As this is the last armada100 platform, remove that support
as well.
Cc: Prafulla Wadaskar <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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We have individual SOC symbols for each keystone 2 platform. Use the
existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to
encompass all of the keystone families.
Signed-off-by: Tom Rini <[email protected]>
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This is actually a misnomer now, since the phandle info may contain
a driver_info index or a udevice index. Rename it to use the word
'phandle', which seems more accurate. Add a comment while we are here.
Also add a test for this function.
Signed-off-by: Simon Glass <[email protected]>
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Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.
Signed-off-by: Simon Glass <[email protected]>
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Use the livetree API for this driver.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.
Signed-off-by: Simon Glass <[email protected]>
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Use this new Kconfig to simplify the compilation conditions where
appropriate.
Signed-off-by: Simon Glass <[email protected]>
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Prepare v2021.10-rc4
Signed-off-by: Tom Rini <[email protected]>
# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <[email protected]>" [ultimate]
# Conflicts:
# board/Arcturus/ucp1020/spl.c
# cmd/mvebu/Kconfig
# common/Kconfig.boot
# common/image-fit.c
# configs/UCP1020_defconfig
# configs/sifive_unmatched_defconfig
# drivers/pci/Kconfig
# include/configs/UCP1020.h
# include/configs/sifive-unmatched.h
# lib/Makefile
# scripts/config_whitelist.txt
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Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.
Check for this situation and use a safe minimal FIFO size instead when
we hit this case.
This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(9faae5457f52).
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Since the beginning of this driver which was initially for the MPC8379
and MPC8536 SoCs, there is this spurious 1ms delay. According to the
comment it should actually be only 8 clock cycles. Esp. during EFI block
transfers, this 1ms add up to a significant delay and slows down EFI
boot.
I couldn't find any mention in the MPC8536 that there should be a delay
of 8 clock cycles between commands. The SD card specification mentions that
the clock has to be left enabled for 8 cycles after a command or
response. But I don't see how this delay will help with this.
Go ahead and just remove it. If there will ever be any regression we can
introduce a compile time flag, but for now I'd like to keep it simple.
In the split off imx driver this delay was also removed in commit
9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending
command").
Signed-off-by: Michael Walle <[email protected]>
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HS400_ES is missed when down grade to HS mode during
device_remove the mmc device
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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When send_status is false or wait_dat0 is not supported, the switch
function should not send CMD13 but directly return.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add support for enumerating MMC card in a given mode using mmc rescan and
mmc dev commands. The speed mode is provided as the last argument in these
commands and is indicated using the index from enum bus_mode in
include/mmc.h. A speed mode can be set only if it has already been enabled
in the device tree.
Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Tested-by: Jaehoon Chung <[email protected]>
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This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59.
In eMMC specification, for the response-with-busy(R1b, R5b)
command, the DAT0 will driven to LOW as BUSY status, and in
sdhci specification, the transfer complete bit should be wait
for BUSY status de-assert.
All response-with-busy commands don't contain data, the data
judgement is no need.
Signed-off-by: Yuezhang.Mo <[email protected]>
Reviewed-by: Andy Wu <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <[email protected]>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.10-rc3
xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012
zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode
versal:
- Add soc driver
sdhci:
- Update tap delay programming for zynq_sdhci driver
cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message
watchdog:
- Fix wwdt compilation
rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver
fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
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Since set_control_reg is available in sdhci.c, use it and remove
arasan_sdhci_set_control_reg().
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable card detect state
host controller is disabling the sd bus voltage to sd card causing
sd card timeout error. So we wait for a maximum of 1000msec to get
the card detect state stable before we enable the sd bus voltage.
This current fix is workaround for now, this needs to be analysed
further. Zynqmp platform should behave the same as Versal, but we
did not encounter this issue as of now. So we are fixing it for
Versal only.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Move tapdelay function calls to zynq_sdhci.c and make them static
inline. zynqmp_tap_delay.h has function prototypes for the functions
defined in tap_delays.c, which will not be needed anymore.
Remove tap_delays.c and zynqmp_tap_delay.h files.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Currently xilinx sdhci driver is using zynqmp_mmio_write() to set
tapdelay values and DLL resets. Continue to use this for SPL and mini
U-Boot where U-Boot will be executed at EL3 level.
Use firmware call xilinx_pm_request() using appropriate arguments to
set input/output tapdelays and also for DLL resets in regular flow(EL2).
Host driver should explicitly request DLL reset before ITAP (assert DLL)
and after OTAP (release DLL) to avoid issues in some cases. Also handle
error return where possible.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This patch adds support for the RK3568 platform to this driver.
Signed-off-by: Yifeng Zhao <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add clock, phy and other configuration, it is convenient to support
new controller. Here a short summary of the changes:
- Add mmc_of_parse to parse dts config.
- Remove OF_PLATDATA related code.
- Reorder header inclusion.
- Add phy ops.
- add ops set_ios_post to modify the parameters of phy when the
clock changes.
- Add execute tuning api for hs200 tuning.
Signed-off-by: Yifeng Zhao <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic.
Signed-off-by: Peng Fan <[email protected]>
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set_delay() has return type as void. If there are any errors while
setting tapdelay's it won't be able to return them.
Change the prototype of set_delay() in sdhci_ops structure and return
the errors from wherever it is called.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Change return type of arasan_sdhci_set_tapdelay() to int, to facilitate
returning errors. Get return values from input and output set clock phase
functions inside arasan_sdhci_set_tapdelay() and return those errors.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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For the eMMC on ST-Ericsson Ux500v2 we need slightly different
configuration values. Use the existing switch statement to match
the peripheral ID of Ux500v2 (0x10480180) and override the necessary
values to make the eMMC work on devices with ST-Ericsson Ux500.
Cc: Linus Walleij <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]> on stm32f769-disco
Reviewed-by: Jaehoon Chung <[email protected]>
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Simplify the code a bit by using the common mmc_of_parse() function
instead of duplicating the device tree parsing code. We can still get
a default value for cfg->f_max by assigning it before calling
mmc_of_parse().
Another advantage of this refactoring is that we parse more properties
now, e.g. "non-removable" can be used to disable CD entirely.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]> on stm32f769-disco
Reviewed-by: Jaehoon Chung <[email protected]>
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Simplify the code a bit by using dev_read_addr_ptr() instead of
dev_read_addr(). This avoids having to cast explicitly to void*.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]> on stm32f769-disco
Reviewed-by: Jaehoon Chung <[email protected]>
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The arm,primecell compatible is used for lots of different types
of devices, e.g. I2C, SPI, coresight, ... We really should not bind
the MMC driver to all of them.
Looking through the device trees in U-Boot there seems to be always
a second compatible string for the pl180 device, either arm,pl180
(already listed) or arm,pl18x. Add the "arm,pl18x" compatible to the
list but remove the generic "arm,primecell".
Note that on Linux these compatibles cannot be found in drivers
because AMBA/primecell devices are matched based on their peripheral ID
instead of the compatible.
This fixes the following error messages when booting the ST-Ericsson
U8500 "stemmy" board with the arm_pl180_mmci driver enabled:
MMC: ptm@801ae000 - probe failed: -38
ptm@801af000 - probe failed: -38
funnel@801a6000 - probe failed: -38
tpiu@80190000 - probe failed: -38
etb@801a4000 - probe failed: -38
Cc: Patrice Chotard <[email protected]>
Fixes: 6f41d1a17e20 ("mmc: arm_pl180_mmci: Sync compatible with kernel")
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Tested-by: Patrice Chotard <[email protected]> on stm32f769-disco
Reviewed-by: Jaehoon Chung <[email protected]>
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Fix mmc_rpmb_route_frames() implementation to comply with most MMC
drivers that expect some alignment of MMC data frames in memory.
When called from drivers/tee/optee/rpmb.c, the address passed is not
aligned properly. OP-TEE OS inserts a 6-byte header before a raw RPMB
frame which makes RPMB data buffer not 32bit aligned. To prevent breaking
ABI with OPTEE-OS RPC memrefs, allocate a temporary buffer to copy the
data into an aligned memory.
Many RPMB drivers implicitly expect 32bit alignment of the eMMC frame
including arm_pl180_mmci.c, sandbox_mmc.c and stm32_sdmmc2.c
Signed-off-by: Timothée Cercueil <[email protected]>
Signed-off-by: Timothée Cercueil <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ti
- Add MMC High speed modes for AM64 and J7200
- Add Sierra/Torrent SERDES driver
- Minor clean-ups for R5F boot from SPL
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Rename these options so that CONFIG_IS_ENABLED can be used with them.
Signed-off-by: Simon Glass <[email protected]>
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Read the strobe select value from the device tree property ti,strobe-sel,
required for HS400 speed mode
Fixes: a20008eabd95 ("mmc: am654_sdhci: Add Support for configuring PHY in J721e")
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Enable HS400 speed mode by writing to HOST_CONTROL2 register.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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All these variables/structure are local and should be static.
Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared. Should it be static?
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Fix these kernel doc warnings:
drivers/mmc/zynq_sdhci.c:181: warning: contents before sections
drivers/mmc/zynq_sdhci.c:236: warning: contents before sections
drivers/mmc/zynq_sdhci.c:291: warning: contents before sections
drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sdcardclk_set_phase'
drivers/mmc/zynq_sdhci.c:354: warning: contents before sections
drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sampleclk_set_phase'
drivers/mmc/zynq_sdhci.c:467: warning: contents before sections
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays
separately. This is required to handle zero values for ITAP and OTAP
values. If we dont split, we will have to remove the if() in the
function, which makes ITAP values to be overwritten when OTAP values are
called to set and vice-versa.
Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6
bits for OTAP for ZynqMP.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Restrict tap_delay value to the allowed size(8bits for itap and 6 bits
for otap) before writing to the tap delay register.
Clear ITAP and OTAP delay bits before updating with the new tap value
for Versal platform.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Allow configuring ITAP and OTAP values with zero to avoid failures in
some cases (one of them is SD boot mode). Legacy, SDR12 modes require
to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104
modes ITAP value is zero.
In SD boot mode firmware configures the SD ITAP and OTAP values and
in this case u-boot has to re-configure required tap values(including zero)
based on the operating mode.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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set_phase() functions are not modifying the ret value and returning
the same uninitialized ret, return 0 instead.
Keep the return type as int to return errors when the tapdelay's are
set via xilinx_pm_request() in future.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support for reading devicetree flags for MMC devices. With this we
can distinguish between fixed and removable drives. Note that this
information is only available when the device is probed, not when it is
bound, since it is read in the of_to_plat() method. This could be changed
if needed later.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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