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ethernet PHY (v4)"
Weijie Gao <[email protected]> says:
This patch adds PHY driver for MediaTek MT7987/MT7988 built-in 2.5Gb
ethernet PHY.
[trini: Change 'tristate' Kconfig to 'bool']
Link: https://lore.kernel.org/r/[email protected]
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The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Prepare v2025.10-rc3
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It's Broadcom PHY simply described as single-port
RGMII 10/100/1000BASE-T PHY.
Signed-off-by: Jim Liu <[email protected]>
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In vsc8514_config there is a while loop for detecting a config failure
using a timeout counter with a post-decrement. In the case of a timeout
this will result in the loop exiting with timeout == -1 so use that as
the test below the loop to detect that the timeout occurred.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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In cs4340_upload_firmware a buffer is allocated with malloc but this is
never freed. The pointer to this buffer, addr, is not even kept
unchanged. But in some cases addr is not a buffer allocated by malloc.
Introduce the use of another pointer to keep track of the buffer and to
know if it needs to be freed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The Auto Negotiation procedure between two Ethernet PHYs consists of
determining the best commonly supported parameters among Speed,
Duplex Mode and Flow Control.
The time taken for this procedure is not only dependent on the local
PHY used, but also on the link-partner PHY.
While a timeout can be specified in the form of a "CONFIG" on the basis
of the local PHY present on the device, since the timeout also depends
on the link-partner PHY, it might be necessary to modify the timeout.
To avoid rebuilding the bootloader for a given device, just because it
may be connected to various link-partner PHYs, each with a different
timeout, introduce an environment variable named "phy_aneg_timeout" and
override "CONFIG_PHY_ANEG_TIMEOUT" with "phy_aneg_timeout".
Signed-off-by: Siddharth Vadapalli <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
[jf: add missing #include <env.h>]
Signed-off-by: Jerome Forissier <[email protected]>
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If phy node isn't found in ethernet-phy subnode, try to get it from
phy-handle. And when this fails, only then use Ethernet node. This
fix results in getting correct phy handle properties for the
phy node if defined.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
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Green Eco"
Romain Gantois <[email protected]> says:
This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:
- Describing the MAC<->PHY link and DP83867 PHY accurately in the device
tree
- Enabling the RGMII1 pinmux configuration
- Enabling the DP83867 driver
These changes are all applied in patch 2.
Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.
Link: https://lore.kernel.org/r/[email protected]
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The DP83867 PHY driver is used by the BeagleBoneGreen Eco board, but adding
it to the am335x-evm defconfig causes SPL to overflow its size limits.
Add a separate option to enable this driver in SPL, so that it can be
enabled in U-Boot without adding unnecessary volume to SPL.
Signed-off-by: Romain Gantois <[email protected]>
Tested-by: Judith Mendez <[email protected]>
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Marek Vasut <[email protected]> says:
Rename the environment related variables and add ENV_ prefix, so that
all configuration options which are related to environment would have
an CONFIG_ENV_ prefix. No functional change.
Link: https://lore.kernel.org/r/[email protected]
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Rename the variable and add ENV_ prefix, so that all configuration
options which are related to environment would have an CONFIG_ENV_
prefix. No functional change.
Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device
index, a number, as enumerated by U-Boot. Update the help text
accordingly.
Signed-off-by: Marek Vasut <[email protected]>
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E Shattow <[email protected]> says:
Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.
There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.
External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.
Link: https://lore.kernel.org/r/[email protected]
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Use consistent lowercase hex prefix style in drivers/*
Does not change hex prefix case in allcaps uppercase style error messages
Signed-off-by: E Shattow <[email protected]>
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Remove unnecessary CL22 phy reset before ethernet phy driver
probe. Lots of ethernet phys requires driver to load firmware.
Before that, CL22 phy reset may lead to malfunction.
Signed-off-by: SkyLake.Huang <[email protected]>
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This was applied prematurely by me as I missed the feedback provided at
the time.
This reverts commit c9c8df2c377e512553f2e9ad5d19c4b85efbf07d.
Signed-off-by: Tom Rini <[email protected]>
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Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The PHY supports
100/1000/2500 Mbps with auto negotiation only.
The driver uses two firmware files, for which updated versions are added to
linux-firmware already.
Based on the Linux upstream 8811 driver code(air_en8811h.c),
I have modified the relevant process to align with the U-Boot boot sequence.
and have validated this on Banana Pi BPI-R3 Mini.
The MD32 FW is currently stored in eMMC partition 1 on Banana Pi BPI-R3 Mini,
and it is loaded from there.
Signed-off-by: Lucien.Jheng <[email protected]>
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We can call phy_modify_mmd() instead of manually calling drv->readext()
and drv->writeext().
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Paul Barker <[email protected]>
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Various signal skew values may be set in the device tree for the ksz9131
Ethernet PHY. For example, the RZ/G2L board requires non-default values
for rxc-skew-psec & txc-skew-psec.
This is based on the ksz9131 phy driver in Linux v6.11.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Paul Barker <[email protected]>
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Micrel KSZ9131 PHY LED behavior is not correct when configured in
Individual Mode, LED1 (Activity LED) is in the ON state when there is
no-link.
Workaround this by setting bit 9 of register 0x1e after verifying that
the LED configuration is Individual Mode.
This issue is described in KSZ9131RNX Silicon Errata DS80000693B [*]
and according to that it will not be corrected in a future silicon
revision.
[*] https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ9131RNX-Silicon-Errata-and-Data-Sheet-Clarification-80000863B.pdf
Based on commit 0316c7e66bbd in the Linux kernel.
Tested-by: Quentin Schulz <[email protected]> # RK3588 Tiger
Signed-off-by: Paul Barker <[email protected]>
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These functions are no longer necessary, remove them.
The struct bb_miiphy_bus is no longer necessary either,
remove it as well.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Access to MDIO bus private data can be provided by both
struct mii_dev .priv member and struct bb_miiphy_bus .priv
member, use the former directly and remove .priv from the
later. Drop unused bb_miiphy_getbus(). This removes any
dependency on struct bb_miiphy_bus from the miiphybb code,
except for helper functions which will be removed later.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The access to struct bb_miiphy_bus_ops via ops pointer in
struct bb_miiphy_bus is not necessary with wrappers added
in previous patch. Pass the ops pointer directly to both
bb_miiphy_read() and bb_miiphy_write() functions.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Move miiphybb operations into separate struct bb_miiphy_bus_ops
structure, add pointer to struct bb_miiphy_bus_ops into the base
struct bb_miiphy_bus and access the ops through this pointer in
miiphybb generic code. The variable reshuffling in miiphybb.c
cannot be easily avoided.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Replace the name based look up in bb_miiphy_getbus() with trivial
container_of() call. This works because the struct bb_miiphy_bus
always embeds the matching struct mii_dev . This also makes the
code much simpler and more efficient.
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Introduce bb_miiphy_alloc()/bb_miiphy_free() wrappers to allocate and free
struct bb_miiphy_bus. Make struct bb_miiphy_bus wrap struct mii_dev, which
will become useful later in bb_miiphy_bus accessors, which would be able
to access struct bb_miiphy_bus using container_of, even if the PHY stack
only passes in the inner struct mii_dev .
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The .init callback is not called by any function, drop it.
There are no more users of the init callback, drop the entire
mechanism.
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Update the debug() print, use __func__ to always print matching
function name, and also print bus name in case there are multiple
busses.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Replace ifdeffery with plain debug() function call. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.
The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.
The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.
Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.
Signed-off-by: Marek Vasut <[email protected]>
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It seems that every remaining system which enables BITBANGMII also
enables BITBANGMII_MULTI . Remove the BITBANGMII_MULTI symbol and
assume it is always enabled. This allows removal of a bit of legacy
code. No functional change intended.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
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Add driver for Motorcomm YT8521S Gigabit ethernet phy.
Signed-off-by: Frank Sae <[email protected]>
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Add driver for Motorcomm YT8531S Gigabit ethernet phy.
Signed-off-by: Frank Sae <[email protected]>
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This reverts commit 431be621c6cbc72efd1d45fa36686a682cbb470a.
Section 3.3 of Reduced Gigabit Media Independent Interface (RGMII)
Version 2.0 (4/1/2002) details that a PHYs using a ~2ns internal delay
are referred to as RGMII-ID. This internal delay is optional.
Page 147-148 of the Marvell Doc. No. MV-S107146-U0 Rev. F details
timings of the RX/TX delays. We see that with the TX/RX_CLK delay
enabled, our RX/TX_CTL signal is shifted w.r.t CLK to reflect the delay
added.
In 431be62 there is no timing difference between RGMII and RGMII-ID, and
so programmers wanting to explicitly set their PHY to RGMII will find
that delay added anyway. This could throw off timing if that internal
delay is undesired.
We should be handling all 4 possible RGMII cases of PHY_INTERFACE_MODE:
RGMII, RGMII_ID, RGMII_TXID, and RGMII_RXID. Reverting 431be62
implements this.
See also m88e1111_config_init_rgmii_delays in the equivalent driver in
Linux (drivers/net/phy/marvell.c), which does not set these delays in
RGMII mode.
68e6eca was tested out on an 88E1512 PHY in RGMII-ID mode. This
reversion has been tested by myself on an 88E1518 in RGMII-ID mode. This
patch affects boards using this driver in "rgmii" mode, as the internal
delay will no longer be enabled. Namely kikwood-nsa310s.
Signed-off-by: Rufus Segar <[email protected]>
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Frank Sae <[email protected]> says:
YT8531 as Gigabit transceiver uses bit15:14(bit9 reserved default 0) as phy
speed mask, YT8821 as 2.5 Gigabit transceiver uses bit9 bit15:14 as phy
speed mask.
Be compatible to YT8821, reform phy speed mask and phy speed macro.
Based on update above, add YT8821 2.5G phy driver.
Link: https://lore.kernel.org/r/[email protected]
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Add a driver for the motorcomm YT8821 2.5G ethernet phy which works in
2500base-x mode.
Verify the driver on BPI-R3(with MediaTek MT7986(Filogic 830) SoC) evb.
Signed-off-by: Frank Sae <[email protected]>
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YT8531 as Gigabit transceiver uses bit15:14(bit9 reserved default 0) as phy
speed mask, YT8821 as 2.5 Gigabit transceiver uses bit9 bit15:14 as phy
speed mask.
Be compatible to YT8821, reform phy speed mask and phy speed macro.
Signed-off-by: Frank Sae <[email protected]>
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Prepare the introduction of the lwIP (lightweight IP) TCP/IP stack by
adding a new net/lwip/ directory and the NET_LWIP symbol. Network
support is either NO_NET, NET (legacy stack) or NET_LWIP. Subsequent
commits will introduce the lwIP code, re-work the NETDEVICE integration
and port some of the NET commands and features to lwIP.
SPL_NET cannot be enabled when NET_LWIP=y. SPL_NET pulls some symbols
that are part of NET (such as arp_init(), arp_timeout_check(),
arp_receive(), net_arp_wait_packet_ip()). lwIP support in SPL may be
added later.
Similarly, DFU_TFTP and FASTBOOT are not compatible with NET_LWIP
because of dependencies on net_loop(), tftp_timeout_ms,
tftp_timeout_count_max and other NET things. Let's add a dependency on
!NET_LWIP for now.
SANDBOX can select NET_LWIP but doing so will currently disable the eth
dm tests as well as the wget tests which have strong dependencies on the
NET code.
Other adjustments to Kconfig files are made to fix "unmet direct
dependencies detected" for USB_FUNCTION_SDP and CMD_FASTBOOT when
the default networking stack is set to NET_LWIP ("default NET_LWIP"
instead of "default NET" in Kconfig).
The networking stack is now a choice between NO_NET,
NET and NET_LWIP. Therefore '# CONFIG_NET is not set' should be
'CONFIG_NO_NET=y'. Adjust the defconfigs accordingly.
Signed-off-by: Jerome Forissier <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
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PHY_NCSI enables drivers/net/phy/ncsi.c which calls net_loop() and
net_set_timeout_handler(). That's the legacy NET stack (as opposed to
NET_LWIP). Therefore add the dependency to Kconfig.
Signed-off-by: Jerome Forissier <[email protected]>
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Switch PHY_ANEG_TIMEOUT to CONFIG_PHY_ANEG_TIMEOUT Kconfig symbol.
This removes one more configuration headers option finalizes its
Kconfig symbol conversion. No functional change expected.
Signed-off-by: Marek Vasut <[email protected]>
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Let users configure default auto-negotiation timeout via Kconfig
instead of specifying it in board configuration headers. This is
the first step toward converting this to Kconfig fully, so far the
legacy PHY_ANEG_TIMEOUT in configuration headers takes precedence.
Signed-off-by: Marek Vasut <[email protected]>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <[email protected]>
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Pull the PHY GPIO reset code into separate function, since
this is and will be reused multiple times. Set up default
reset assert and deassert timing to generous 20ms and 1ms
for maximum compatibility in case those DT properties are
missing.
Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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From the ethernet header is not on aligned, because the length
of the ethernet header is 14 bytes.
Therefore, unaligned access must be done here.
Signed-off-by: Jacky Chou <[email protected]>
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There is no need to perform the endian twice here.
Signed-off-by: Jacky Chou <[email protected]>
Reviewed-by: Dan Carpenter <[email protected]>
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As with fixed-link phy device, the NC-SI phy devive does not
require an mdio bus. So, a condition is added to check the
NC-SI phy id to avoid accessing the bus pointer that is NULL.
Signed-off-by: Jacky Chou <[email protected]>
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Booting R-Car Gen3 arm64 U-Boot with CONFIG_UBSAN=y resulted in:
=====================================================================
UBSAN: Undefined behaviour in drivers/net/phy/phy.c:728:19
left shift of 1 by 31 places cannot be represented in type 'int'
=====================================================================
Fix it by appending the UL suffix to the numeric literal. While at it,
convert the type of "addr" variable from signed to unsigned, to protect
against shifting the numeric literal by a negative value (which would
lead to yet another undefined behavior).
Fixes: 1adb406b0141 ("phy: add phy_find_by_mask/phy_connect_dev")
Signed-off-by: Eugeniu Rosca <[email protected]>
* Using U-suffix for integer is sufficient.
* ffs() of non-zero value cannot be 0. But addr being unsigned is
* preferable.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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