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The variable 'res' may be unused uninitialized if our call to
mv88e61xx_port_read (register read) fails and we goto the error
handling section. In this case we set 'res' to -EIO to indicate why we
failed.
Cc: Joe Hershberger <[email protected]>
Cc: Chris Packham <[email protected]>
Cc: Kevin Smith <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h
Signed-off-by: Tom Rini <[email protected]>
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This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).
For this purpose we introduce a new phy-driver, called "Fixed PHY".
Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.
Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).
During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.
Signed-off-by: Hannes Schmelzer <[email protected]>
Signed-off-by: Hannes Schmelzer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: John Haechten <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <[email protected]>
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Provide the necessary Kconfig symbols so that PHYLIB support may be
enabled in Kconfig, as opposed to needing to #define these symbols in
C source headers.
BITBANGMII and MV88E6352_SWITCH are left out of the PHYLIB submenu as
they don't seem to explicitly depend on it (i.e. they do not use the
phy_driver class).
Signed-off-by: Alexandru Gagniuc <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Use some constants for the phy configuration instead of so many magic
numbers.
Signed-off-by: Joe Hershberger <[email protected]>
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Add support for programmable MAC impedance configuration and
fix typo in DT impedance parameters names.
Signed-off-by: Mugunthan V N <[email protected]>
Signed-off-by: Grygorii Strashko <[email protected]>
Tested-by: Lokesh Vutla <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 79e86ccb3786c8b20004db3fa10a70049456f580 "vitesse: remove duplicated
argument to ||" correctly removed a redundant check.
However, I believe that the original code was simply wrong, and should have
been checking against RGMII_ID.
To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This device also works with the 88E1518 code, so we just adjust
the UID mask accordingly.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The mask for the 88E1510 meant that the 88E1518 code would never be
used.
Signed-off-by: Phil Edworthy <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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There is code that is specifically for RGMII_TXID interface, but this
will never get used because the code checks that the RGMII interface
is RGMII_ID to RGMII_RXID; RGMII_TXID is after this.
To fix this and avoid similar problems in the future, use the
phy_interface_is_rgmii helper function.
Signed-off-by: Phil Edworthy <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add support for Marvell 88E1680 Integrated Octal
10/100/1000 Mbps Energy Efficient Ethernet Transceiver.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds support for SMSC LAN8742 in phylib
Signed-off-by: Michael Kurz <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.
Signed-off-by: Kamensky Ivan <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.
Tested on custom board with AM3352 SOC and VSC801 PHY.
Signed-off-by: Alexandru Gagniuc <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms
specified by the IEEE802.3 standard from the chip's default of 8ms.
For more details, see the "Auto-Negotiation Timing" section of the
KSZ9031RNX datasheet.
[1] https://patchwork.kernel.org/patch/6558371/
Signed-off-by: Ash Charles <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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On some boards these switches are wired directly into a SERDES
interface on another Ethernet MAC. Add the ability to specify
these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines
a bit mask of these fixed ports.
Signed-off-by: Chris Packham <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The Marvell Link Street mv88e60xx is a series of FastEthernet switch
chips, some of which also support Gigabit ports. It is similar to the
mv88e61xx series which support Gigabit on all ports.
The main difference is the number of ports. Which affects the
PORT_COUNT define and the size of the mask passed to
mv88e61xx_port_set_vlan().
Other than that it's just a matter of adding the appropriate chip
IDs.
Signed-off-by: Chris Packham <[email protected]>
Cc: Joshua Scott <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.
Reviewed-by: Sekhar Nori <[email protected]>
Signed-off-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This adds support for internal delay on RX and TX on RGMII interface for the
AR8035 phy.
This is basically the same Linux driver do. Tested on a Zynq Zturn board (for
which u-boot support in is my tree; first patch waiting ML approval)
Signed-off-by: Andrea Merello <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <[email protected]>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <[email protected]>
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If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.
Make those changes manually.
Signed-off-by: Joe Hershberger <[email protected]>
For the 4xx related files:
Acked-by: Stefan Roese <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This corrects a build error on zynqmp.
Signed-off-by: Simon Glass <[email protected]>
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This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch adds a phy driver for the Micrel KSZ886x switches.
Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.
KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)
This patch supports only unmanaged and MIIM modes.
Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.
Verified with the KSZ8863MLL.
Signed-off-by: Alexey Firago <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: Scott Wood <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
drivers/net/zynq_gem.c
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The code assumed that if the interface is not RGMII configured
then it must be SGMII configured. This device has the ability
to support most of the MII interfaces. Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.
This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree. If the value is not set in the
devicetree then set the delay to the default.
If devicetree is not used then use the default defines within the
driver.
Signed-off-by: Dan Murphy <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot. This is a complete
rework to support this device as a PHY.
Signed-off-by: Kevin Smith <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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No boards are using this driver. Remove in preparation for a new
driver with integrated PHY support.
Signed-off-by: Kevin Smith <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
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The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: Michal Simek <[email protected]>
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Fix zynq_gem driver to handle error from phy_config correctly.
Signed-off-by: Michal Simek <[email protected]>
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Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Return -ETIMEDOUT if timeout happens.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add phy driver support for xilinx PCS/PMA core
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Kedareswara rao Appana <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.
After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.
Fix this by setting the full PHY ID in the RTL8211B_driver uid field.
Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: Karsten Merker <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.
This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.
There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]
Signed-off-by: Michael Haas <[email protected]>
Tested-by: Karsten Merker <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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In commit <a058052c358c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.
To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.
Signed-off-by: Alison Wang <[email protected]>
Acked-by: Stefan Agner <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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