| Age | Commit message (Collapse) | Author |
|---|
|
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call.
Converted using sed
"s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {"
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
Introduce U_BOOT_PHY_DRIVER() macro which is used to add struct phy_driver
into a new linker list section containing all compiled in struct phy_driver
drivers. This is so far empty until PHY drivers are converted over to this
macro.
Iterate over both drivers registered using soon to be legacy phy_register()
as well as drivers in the new linker list when looking up a suitable PHY
driver. This way, PHY drivers can be converted over to the new macro one
driver at a time.
The relocation of callbacks for linker list based drivers now happens in
phy_init() call as the drivers are available at that point in time, and
phy_register() is not called for those drivers.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
Create separate function to implement manual relocation of PHY driver
functions and make use of that function. This is a preparatory patch
for introduction of PHY driver definition using linker lists.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
|
|
These struct phy_driver ... instances are local to this source code
file, staticize them. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Michal Simek <[email protected]>
Tested-by: Michal Simek <[email protected]> #microblaze (MANUAL_RELOC)
Reviewed-by: Ramon Fried <[email protected]>
|
|
Add a new SPL_PHY_ATHEROS to avoid a build error on am335x_evm with split
config.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move
the comment from code to the help to explain what this does.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Perform a simple rename of CONFIG_PHY_ET1011C_TX_CLK_FIX to CFG_PHY_ET1011C_TX_CLK_FIX
Signed-off-by: Tom Rini <[email protected]>
|
|
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.
Signed-off-by: Tom Rini <[email protected]>
|
|
With DM_ETH being required now for all drivers, we don't need this
listed on individual drivers as well.
Signed-off-by: Tom Rini <[email protected]>
|
|
Add a driver for the Intel XWAY GbE PHY:
- configure RGMII using dt phy-mode and standard delay properties
- use genphy_config
Signed-off-by: Tim Harvey <[email protected]>
|
|
Fix a couple of typos:
- s/Acquantia/Aquantia/
- s/firmare/firmware/
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.
Signed-off-by: Samuel Mendoza-Jonas <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
We check if phydev is NULL. Only but if it is non-NULL we set one
component of phydev. But even if it is NULL we set another. We should not
dereference NULL in either case.
Fixes: e24b58f5ed4f ("net: phy: don't require PHY interface mode during PHY creation")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
|
|
The convinience functions are not that small and they caused
bloated text segments because of their usage.
There was no need to inline them in the first place, as
they're not part of a fastpath.
Signed-off-by: Ramon Fried <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
|
|
This patch adds basic support for the Marvell 88E1240 PHY.
This will be used by the upcoming ethernet support addition for the
Marvell MIPS Octeon EBB7304 platform.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
|
|
This patch adds support for the "marvell,reg-init" DT property, which
is used to describe board specific Marvell PHY register configurations
in the board dts file. This DT property is supported in the Linux Kernel
since a longer time. Adding it to U-Boot now, enables the boards which
describe the register settings in their DT files here as well.
I've included calling this marvell_of_reg_init() to all foo_config()
functions in this patch as well. If CONFIG_DM_ETH is not set, there is
no ofnode, or no "marvell,reg-init" property, the PHY initialization is
unchanged.
The function marvell_of_reg_init() is a port of the Linux version.
Please note that I explicitly did not add error checking and handling
to the U-Boot version, as this is basically not done for phy_read/write
in this Marvell PHY code.
This will be used by the upcoming ethernet support on the MIPS
Octeon EBB 7304 board.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
Cc: Marek Behún <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
|
|
This converts the following to Kconfig:
CONFIG_FSL_MEMAC
CONFIG_SYS_MEMAC_LITTLE_ENDIAN
Signed-off-by: Tom Rini <[email protected]>
|
|
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as
well as providing the reference clock on CLK25_REF.
Add support for selecting the clock via device-tree properties.
This patch is based on the Linux implementation for this feature,
which has been added to netdev/net-next.git [1].
[2] https://patchwork.kernel.org/project/netdevbpf/cover/[email protected]/
Signed-off-by: Josua Mayer <[email protected]>
|
|
Currently, the adin driver fails to compile.
The original patch introducing the adin driver used the function
phy_get_interface_by_name to support the adi,phy-mode-override
property. Unfortunately, a few days before the adin patch
was accepted, another patch removed support for phy_get_interface_by_name:
https://github.com/u-boot/u-boot/commit/123ca114e07ecf28aa2538748d733e2b22d8b8b5
This patch refactors adin_get_phy_mode_override, implementing the logic in
the new function, ofnode_read_phy_mode, from the patch above.
Signed-off-by: Nate Drude <[email protected]>
Tested-by: Josua Mayer <[email protected]>
Signed-off-by: Josua Mayer <[email protected]>
|
|
- DM9000 DM support
- tftp server bug fix
- mdio ofnode support functions
- Various phy fixes and improvements.
[trini: Fixup merge conflicts in drivers/net/phy/ethernet_id.c
drivers/net/phy/phy.c include/phy.h]
|
|
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Ariel D'Alessandro <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Add read-modify-write unlocked accessor for accessing a PHY register.
Signed-off-by: Ariel D'Alessandro <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
This driver supports NXP C45 TJA11XX PHYs, but there're also other NXP
TJA11XX PHYs. Let's rename functions in this driver to be c45 variant
specific, so further drivers can be introduced adding support for NXP
TJA11XX PHYs.
Signed-off-by: Ariel D'Alessandro <[email protected]>
|
|
The current implementation configures RGMII using device tree phy-mode
property and then calls genphy_config
adin_config_rgmii_mode is derived from:
https://github.com/varigit/linux-imx/blob/lf-5.10.y_var04/drivers/net/phy/adin.c#L218-L262
Signed-off-by: Nate Drude <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Currently we require PHY interface mode to be known when
finding/creating the PHY - the functions
* phy_connect_phy_id()
* phy_device_create()
* create_phy_by_mask()
* search_for_existing_phy()
* get_phy_device_by_mask()
* phy_find_by_mask()
all require the interface parameter, but the only thing done with it is
that it is assigned to phydev->interface.
This makes it impossible to find a PHY device without overwriting the
set mode.
Since the interface mode is not used during .probe() and should be used
at first in .config(), drop the interface parameter from these
functions. Make the default value of phydev->interface (in
phy_device_create()) to be PHY_INTERFACE_MODE_NA. Move the interface
parameter to phy_connect_dev(), where it should be.
Change all occurrences treewide. In occurrences where we don't call
phy_connect_dev() for some reason (they only configure the PHY without
connecting it to an ethernet controller), set
phydev->interface = value from phy_find_by_mask call.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
|
|
Use phydev->is_c45 instead of is_10g_interface(phydev->interface) to
determine whether clause 45 protocol should be used.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
We want to be able to have phydev->interface uninitialized during
->probe(). We should assume that phydev->interface is initialized only
before ->config().
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Rename constant PHY_INTERFACE_MODE_COUNT to PHY_INTERFACE_MODE_MAX to
make it compatible with Linux' naming.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
|
|
Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the
"phy-mode" / "phy-connection-type" property. Add corresponding UT test.
Use them treewide.
This allows us to inline the phy_get_interface_by_name() into
ofnode_read_phy_mode(), since the former is not used anymore.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
|
|
The "phy-interface-type" property should be "phy-connection-type".
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
|
|
The type of the return value of phy_read() and phy_read_mmd() is int.
Change the variable to not be unsigned so that we not get into an
unsigned compared against 0.
Signed-off-by: Haolin Li <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO
bus which is not specified in the device tree, as evidenced by:
pfe_eth_probe
-> pfe_phy_configure
-> phy_connect
When this happens, the PHY will have an invalid OF node.
When ar803x_config() runs, it silently fails at ar803x_of_init(), and
therefore, fails to run the rest of the initialization.
This makes MII_BMCR contain what it had after BMCR_RESET (0x8000) has
been written into it by phy_reset(). Since BMCR_RESET is volatile and
self-clearing, the MII_BMCR ends up having a value of 0x0. The further
configuration of this register, which is supposed to be handled by
genphy_config_aneg() lower in ar803x_config(), never gets a chance to
run due to this early error from ar803x_of_init().
As a result of having MII_BMCR as 0, the following symptom appears:
=> setenv ethact pfe_eth0
=> setenv ipaddr 10.0.0.1
=> ping 10.0.0.2
pfe_eth0 Waiting for PHY auto negotiation to complete......... TIMEOUT !
Could not initialize PHY pfe_eth0
Manually writing 0x1140 into register 0 of the PHY makes the connection
work, but it is rather desirable that the port works without any manual
intervention.
Fixes: fe6293a80959 ("phy: atheros: add device tree bindings and config")
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
A DM_ETH driver may use phy_connect() towards a PHY address on an MDIO
bus which is not specified in the device tree, as evidenced by:
pfe_eth_probe
-> pfe_phy_configure
-> phy_connect
When this happens, the PHY will have an invalid OF node.
The dp83867_config() method has extra initialization steps which are
bypassed when the PHY lacks an OF node, which is undesirable because it
will lead to broken networking. Allow the rest of the code to run.
Fixes: 085445ca4104 ("net: phy: ti: Allow the driver to be more configurable")
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc1 v2
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
|
|
If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the
eth-phy-uclass driver, so use the PHY gpio reset functionality from
ethernet_id file when this config is disabled to reset the PHY.
Use debug() print instead of dev_err() to avoid warning incase if phy-id
compatible string is not present.
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/4d0fd3f9f886c1d943776025e5efb5438b0eb389.1648631275.git.michal.simek@xilinx.com
|
|
While creating a phy device using phy_device_create(), we need to
provide a valid phyaddr instead of 0 causing phy address being
registered as 0 with mdio bus and shows mdio phy list as below
ZynqMP> mdio list
eth0:
0 - TI DP83867 <--> ethernet@ff0b0000
eth1:
0 - TI DP83867 <--> ethernet@ff0c0000
Also PHY soft reset is being requested on 0 instead of valid
address causing "PHY reset timed out" error.
So add phyaddr argument to phy_connect_phy_id() and to its prototype
to create phy device with valid phyaddress.
Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset")
Signed-off-by: T Karthik Reddy <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com
|
|
This converts the following to Kconfig:
CONFIG_BITBANGMII_MULTI
Signed-off-by: Tom Rini <[email protected]>
|
|
This converts the following to Kconfig:
CONFIG_PHY_RESET_DELAY
Cc: Ramon Fried <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
Ethernet phy like dp83867 is using strapping resistors to setup PHY
address. On Xilinx boards strapping is setup on wires which are connected
to SOC where internal pull ups/downs influnce phy address. That's why there
is a need to setup pins properly (via pinctrl driver for example) and then
perform phy reset. I can be workarounded by reset gpio done for mdio bus
but this is not working properly when multiply phys sitting on the same
bus. That's why it needs to be done via ethernet-phy-id driver where dt
binding has gpio reset per phy.
DT binding is available here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml
The driver is are reading the vendor and device id from valid phy node
using ofnode_read_eth_phy_id() and creating a phy device.
Kconfig PHY_ETHERNET_ID symbol is used because not every platform has gpio
support.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: T Karthik Reddy <[email protected]>
Link: https://lore.kernel.org/r/70ab7d71c812b2c972d48c129e416c921af0d7f5.1645627539.git.michal.simek@xilinx.com
|
|
Remove static return type for phy_device_create() to avoid file scope for
this function. Also add required prototype in phy.h.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: T Karthik Reddy <[email protected]>
Link: https://lore.kernel.org/r/1517f4053403fbd53e899d500e7485d068a4f0b6.1645627539.git.michal.simek@xilinx.com
|
|
This driver is based on an older downstream TI kernel, with
changes and cleanups to work with mainline device-tree bindings.
Signed-off-by: Dominic Rath <[email protected]>
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
This converts the following to Kconfig:
CONFIG_ENV_SPI_BUS
CONFIG_ENV_SPI_CS
CONFIG_ENV_SPI_MAX_HZ
CONFIG_ENV_SPI_MODE
As part of this, we use Kconfig to provide the defaults now that were
done in include/spi_flash.h. We also in some cases change from using
CONFIG_ENV_SPI_FOO to CONFIG_SF_DEFAULT_FOO as those were the values in
use anyhow as ENV was not enabled.
Signed-off-by: Tom Rini <[email protected]>
|
|
Some boards need to change the tx/rx delay config in order for
gigabit Ethernet to work.
In Linux commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), Realtek documented the bits for overriding the delays
from the hardware straps.
Copy the logic from linux, so the delay config is set from the PHY's
interface type (the phy-mode property in the device tree).
This removes the need for a one-off workaround for the Pine A64+ board.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
The VSC8502 is a Microchip (formerly Microsemi, formerly Vitesse)
dual port, gigabit Ethernet copper PHY which supports the MII, GMII and
RGMII MAC-side interfaces.
Of these, I could only test RGMII, and my board needed RGMII delays to
be applied by software, so I am able to confirm that this patch handles
that properly.
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
|
Signed-off-by: Wolfgang Denk <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-net into next
- Fix some non-NULL terminated strings in the networking subsystem
- net: tsec: Mark tsec_get_interface as __maybe_unused
|
|
After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/
which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/[email protected]/
and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.
So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.
As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.
This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.
Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.
NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".
Signed-off-by: Vladimir Oltean <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
|
