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Signed-off-by: Albert ARIBAUD <[email protected]>
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This required manual merging drivers/mtd/nand/Makefile
and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
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SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek <[email protected]>
CC: Andy Fleming <[email protected]>
CC: Zang Roy-R61911 <[email protected]>
CC: Kumar Gala <[email protected]>
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In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.
Signed-off-by: Ruchika Gupta <[email protected]>
Signed-off-by: Vakul Garg <[email protected]>
Acked-by: Roy Zang <[email protected]>
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Signed-off-by: Yegor Yefremov <[email protected]>
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The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?
Signed-off-by: Kim Phillips <[email protected]>
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bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?
Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.
Signed-off-by: Kim Phillips <[email protected]>
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u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <[email protected]>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <[email protected]>
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This stuff has been rotting in the tree for a while now. Remove it.
Signed-off-by: Marek Vasut <[email protected]>
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TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.
struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
Signed-off-by: Sandeep Singh <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The following warning was produced, fix it:
mcfmii.c: In function 'mcffec_miiphy_write':
mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <[email protected]>
Cc: "Jin Zhengxiong-R64188" <[email protected]>
Cc: Jason Jin <[email protected]>
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As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.
Signed-off-by: Stefan Roese <[email protected]>
Cc: James MacAulay <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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negotiation is enabled in RMII mode. Some boards based on da850 need
to suppress this procedure.
CC: Rajashekhara, Sudhakar <[email protected]>
CC: Lad, Prabhakar <[email protected]>
CC: Hadli, Manjunath <[email protected]>
CC: [email protected]
Acked-by: Stefano Babic <[email protected]>
CC: Tom Rini <[email protected]>
Signed-off-by: Bastian Ruppert <[email protected]>
Acked-by: Prabhakar Lad <[email protected]>
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Replace the magic contant 1 << 24 with properly defined bits.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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The mechanism waiting for transmission to finish in fec_send() now
relies on the E-bit being cleared in the TX buffer descriptor. In
case of data cache being on, this means invalidation of data cache
above this TX buffer descriptor on each test for the E-bit being
cleared.
Apparently, there is another way to check if the transmission did
complete. This is by checking the TDAR bit in the X_DES_ACTIVE
register. Reading a register does not need any data cache invalidation,
which is beneficial.
Rework the sequence that wait for completion of the transmission so that
the TDAR bit is tested first and afterwards check the E-bit being clear.
This cuts down the number of cache invalidation calls to one.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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Align the address that's to be invalidated/flushed properly.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Do not pass unaligned RX buffer to the upper layers. The upper layer,
especially in the ARP case, recycles the buffer and passes it back into
the FEC, into it's TX path. With caches enabled, the FEC hangs on this
from time to time.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Joe Hershberger <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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-VSC8662 is Dual Port 10/100/1000Base-T Phy,
100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.
-Its register set and features are similar to
other Vitesse Phys
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: York Sun <[email protected]>
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This patch add support for the configuration of an external switch from
the 88E6xxx series from Marvell trough an MDIO link using indirect
adressing. This can be used if we do not want to use an EEPROM for the
configuration.
This driver is not generic and was not tested on other switches than the
88e6352. This is proposed as a first implementation that is somewhat
limited but works and that can be used as a basis for further
developments for this switch family.
Signed-off-by: Valentin Longchamp <[email protected]>
cc: Holger Brunck <[email protected]>
cc: Prafulla Wadaskar <[email protected]>
cc: Joe Hershberger <[email protected]>
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Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Marek Vasut <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Check the incoming packets' source IP address... if ncip isn't set to a
broadcast address, only listen to the client at ncip.
Signed-off-by: Joe Hershberger <[email protected]>
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Refresh the netconsole settings from the env before each packet instead
of only on netconsole init.
Signed-off-by: Joe Hershberger <[email protected]>
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Previously u-boot would initialize the network interface for every
network operation and then shut it down again. This makes sense for
most operations where the network in not known to be needed soon after
the operation is complete. In the case of netconsole, it will use the
network for every interaction with the shell or every printf. This
means that the network is being reinitialized very often. On many
devices, this intialization is very slow.
This patch checks for consecutive netconsole actions and leaves the
ethernet hardware initialized between them. It will still behave the
same old way for all other network operations and any time another
network operation happens between netconsole operations.
Signed-off-by: Joe Hershberger <[email protected]>
Cc: Stefano Babic <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Allow a board to configure a larger buffer for netconsole, but leave
the default.
Signed-off-by: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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R8A7740 of rmobile has ethernet device, and this is same IP of
sh-ether. This support R8A7740 of rmobile.
Signed-off-by: Hideyuki Sano <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Apply the following questionable adjustment to silence GCC.
armada100_fec.c: In function ‘armdfec_send’:
armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
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Support new CONFIG_OF_CONTROL option where device
probing is done based on device tree description.
Signed-off-by: Michal Simek <[email protected]>
CC: Joe Hershberger <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Bryan Hundven <[email protected]>
Cc: Michael Schwingen <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: U-Boot DM <[email protected]>
Cc: Joe Hershberger <[email protected]>
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It is desirable to use different port numbers for sending and receiving
packets with netconsole in the case where you have more than one device
on the local subnet with netconsole enabled for broadcast. When they
use the same port for both, any output from one will look like input to
the other. This is typlically not desirable.
This patch allows the input and output ports to be specified separately
in the environment.
Signed-off-by: Joe Hershberger <[email protected]>
Cc: Mike Frysinger <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Daniel Hellstrom <[email protected]>
Cc: [email protected]
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* 'master' of git://git.denx.de/u-boot-avr32:
net:macb: add line break
avr32:portmux: fix setup for macb1
avr32: Remove redundant LDSCRIPT definition
Signed-off-by: Wolfgang Denk <[email protected]>
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Without this patch we see annoying output like this:
---8<---
U-Boot> dhcp
macb1: PHY not foundmacb0: PHY present at 1
macb0: Starting autonegotiation...
--->8---
Signed-off-by: Andreas Bießmann <[email protected]>
cc: Joe Hershberger <[email protected]>
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Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <[email protected]>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <[email protected]>
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CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <[email protected]>
Signed-off-by: Chandan Nath <[email protected]>
Signed-off-by: Satyanarayana, Sandhya <[email protected]>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok <[email protected]>
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These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <[email protected]>
Acked-by: Kumar Gala <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <[email protected]>
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SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's
GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757,
the driver handles the GETHER.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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The previous code had many similar definitions in each CPU.
This patch borrows from the sh_eth driver of Linux kernel.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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