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Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the
checking for ESTATUS_1000_XHALF, but it incorrectly sets the
SUPPORTED_1000baseX_Full flag in this case.
Set the SUPPORTED_1000baseX_Half flag instead.
Acked-by: Charles Coldwell <[email protected]>
Reviewed-By: Sascha Silbe <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
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de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a
check for the extended status register in order to support
1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since
Extended Status only indicates what the PHY (i.e. the local side) is
capable of, this broke communication with non-1Gbps peers.
Only check the extended status if the 1000BASE-T registers are
actually missing so we don't end up setting speed to 1Gbps even though
the previous test (for the combination of local and peer support for
1Gbps) already indicated we can't do 1Gbps with the current peer.
Signed-off-by: Sascha Silbe <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
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Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.
Conflicts:
arch/arm/dts/exynos5250.dtsi
Signed-off-by: Tom Rini <[email protected]>
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The MX28 multi-layer AHB bus can be too slow and trigger the
FEC DMA too early, before all the data hit the DRAM. This patch
ensures the data are written in the RAM before the DMA starts.
Please see the comment in the patch for full details.
This patch was produced with an amazing help from Albert Aribaud,
who pointed out it can possibly be such a bus synchronisation
issue.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
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Remove incorrectly called and duplicate flush_dcache_range() call
from fec_mxc driver. The call is not needed, since the caches are
already flushed in fec_tbd_init(), moreover the second argument should
be the ending address, not size.
Signed-off-by: Marek Vasut <[email protected]>
Reported-by: Albert Aribaud <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tom Rini <[email protected]>
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add atheros ar803x phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
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add natsemi dp83630 phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <[email protected]>
Cc: Andy Fleming <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Signed-off-by: Kuo-Jung Su <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Tom Rini <[email protected]>
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Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid!!!
Signed-off-by: Kuo-Jung Su <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Tom Rini <[email protected]>
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Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read
Signed-off-by: Leo Sartre <[email protected]>
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Add gigabit MAC support in macb driver
- using IP version to distinguish whether MAC is GMAC
Signed-off-by: Bo Shen <[email protected]>
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using phylib to configure phy device in macb driver
Signed-off-by: Bo Shen <[email protected]>
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Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC
Signed-off-by: Bo Shen <[email protected]>
Acked-by: Andreas Bießmann <[email protected]>
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The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.
Signed-off-by: Roberto Cerati <[email protected]>
Signed-off-by: Raffaele Recalcati <[email protected]>
[[email protected]: address comments from review results]
[[email protected]: clean up for submit]
Signed-off-by: Bo Shen <[email protected]>
Tested-by: Raffaele Recalcati <[email protected]>
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Signed-off-by: Xie Xiaobo <[email protected]>
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commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <[email protected]>
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell <[email protected]>
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Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication
Signed-off-by: David Andrey <[email protected]>
Cc: Troy Kisky <[email protected]>
Cc: Joe Herschberger <[email protected]>
Cc: Andy Fleming <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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The added weak symbol must not be static.
This was introduced in 416ce623fbad51af57660346ebb6f7befb88b3c9
Signed-off-by: Joe Hershberger <[email protected]>
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SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim <[email protected]>
Signed-off-by: Vipin Kumar <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Do not select MIIPORT for RGMII interface
Signed-off-by: Vipin Kumar <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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This add phylib support to the Marvell GBE driver.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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This adds PHY initialization for Marvell Alaska 88E1310 PHY.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c
Signed-off-by: Yegor Yefremov <[email protected]>
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Signed-off-by: Yegor Yefremov <[email protected]>
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This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.
From: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Signed-off-by: Henrik Nordstrom <[email protected]>
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Conflicts:
drivers/serial/Makefile
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This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: Benoit Thebaudeau <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
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Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
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- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.
Signed-off-by: Masahiro Yamada <[email protected]>
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The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.
Signed-off-by: Shengzhou Liu <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Sonic Zhang <[email protected]>
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Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.
Signed-off-by: Matt Porter <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.
Signed-off-by: Matt Porter <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <[email protected]>
Reported-by: John Traill <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Autodetect phy if phyaddress is setup to -1.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO
Do not enable emio for this standard board configuration for now.
Signed-off-by: David Andrey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: David Andrey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.
This patch solves the problem with repeatable tftp transfers.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Remove one return from the code.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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