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Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <[email protected]>
Cc: Joe Hershberger <[email protected]>
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch adds a phy driver for the Micrel KSZ886x switches.
Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.
KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)
This patch supports only unmanaged and MIIM modes.
Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.
Verified with the KSZ8863MLL.
Signed-off-by: Alexey Firago <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The rtl8169 driver uses a global variable to store the register address
of the adapter being operated upon. This is updated to point at the
correct adapter when sending or receiving a packet, or shutting down the
adapter, but not when initializing the adapter. Consequently, switching
between different adapters within the same U-Boot runtime does not work
correctly since the driver programs the wrong registers during
rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start().
Note that since rtl8169_eth_stop() does set the global variable, the
second consecutive attempt to use the "new" adapter did work even before
this patch, because each time network usage is shut down, the network
core calls stop, which sets the variable so that the next start does
actually initialize the hardware, and the adapter works.
Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so
if using only a single device, or if picking the "right" device (based on
probe order) when multiple devices are present, ioaddr will already be set
correctly from the get-go, so the issue does not occur.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add driver-model support to this driver. The old code remains for now so
that we can convert boards one at a time.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Adjust this driver to avoid using struct netdev in functions that driver
model will call. Also refactor the receive function to be compatible with
driver model.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: Scott Wood <[email protected]>
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Add ethernet driver for the AR933x and AR934x Atheros MIPS machines.
The driver could be easily extended to other WiSoCs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Wills Wang <[email protected]>
[fixed Kconfig dependency]
Signed-off-by: Daniel Schwierzeck <[email protected]>
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If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.
Signed-off-by: Paul Burton <[email protected]>
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Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.
Signed-off-by: Paul Burton <[email protected]>
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All members of the DMA descriptor must be 32-bit, even on 64-bit
architectures: change the type to u32 to ensure this. Also, fix
other warnings.
Signed-off-by: Beniamino Galvani <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
[trini: Use phys_addr_t not unsigned long long to test that we're within
DMA'able memory]
Signed-off-by: Tom Rini <[email protected]>
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Add support for the snps,reset-gpio, snps,reset-active-low (optional) and
snps,reset-delays-us device-tree bindings. The combination of these
three define how the PHY should be reset to ensure it's in a sane state.
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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some case
When using rcw protocols to support 10G on MAC9 and MAC10, these MACs
should not be identified as 1G interface, otherwise, one MAC will be
listed as two Ethernet ports. For example, MAC9 will be listed as
FM1@TGEC1 and FM1@DTSEC9.
Signed-off-by: Ying Zhang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
drivers/net/zynq_gem.c
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The code assumed that if the interface is not RGMII configured
then it must be SGMII configured. This device has the ability
to support most of the MII interfaces. Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.
This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree. If the value is not set in the
devicetree then set the delay to the default.
If devicetree is not used then use the default defines within the
driver.
Signed-off-by: Dan Murphy <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add the ability to pass the phy-handle node offset
to the phy driver. This allows the phy driver
to access the DT subnode's data and parse accordingly.
Signed-off-by: Dan Murphy <[email protected]>
Tested-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add the ability to read the phy-handle node of the
cpsw slave. Upon reading this handle the phy-id
can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.
Signed-off-by: Dan Murphy <[email protected]>
Tested-by: Mugunthan V N <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.
The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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On some boards number of slaves can be 1 when only one port
ethernet is pinned out. So do not break when slave_index and
num slaves check fails, instead continue to parse the next
child.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot. This is a complete
rework to support this device as a PHY.
Signed-off-by: Kevin Smith <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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No boards are using this driver. Remove in preparation for a new
driver with integrated PHY support.
Signed-off-by: Kevin Smith <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Cc: Prafulla Wadaskar <[email protected]>
Cc: Albert ARIBAUD <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Marek Vasut <[email protected]>
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Use simpler runtime cpu dection macros.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Joe Hershberger <[email protected]>
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The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: Michal Simek <[email protected]>
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Fix zynq_gem driver to handle error from phy_config correctly.
Signed-off-by: Michal Simek <[email protected]>
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Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Return -ETIMEDOUT if timeout happens.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Handle error returned by phy_startup() properly.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Spelling corrections for (among other things):
* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
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Memset pools_params as "0" to avoid garbage value in dpni_set_pools.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reported-by: Jose Rivera <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Signed-off-by: Vagrant Cascadian <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <[email protected]>
CC: Prabhakar Kushwaha <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Signed-off-by: Codrin Ciubotariu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Some SerDes protocols might not enable all l2switch ports. In this case,
these ports should not be configured to perform Rx/Tx operations.
This also fixes an issue when flooded frames were also switched to
disabled ports and frames start to accumulate, consuming memory
and eventually causing head-of-line blocking for other frames.
Signed-off-by: Codrin Ciubotariu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: York Sun <[email protected]>
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PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Do not use debug() when printing error message. Use printf instead.
Signed-off-by: Michal Simek <[email protected]>
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Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <[email protected]> # driver part
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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