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Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The spatch series converting legacy drivers from miiphy_register to
mdio_register changed the return convention of the davinci_emac internal
MDIO accessors, making the internal code relying on it misbehaving:
no mdiodev get registered and U-Boot crashes when using net cmds in the
context of the old legacy net API.
ATM davinci_emac_initialize and cpu_eth_init don't return a proper value
in that case but fixing them would not avoid the crash.
This change is just a follow-up to the spatch pass, the MDIO accessors
of the mdiodev introduced by the spatch pass retain their proper values.
Signed-off-by: Karl Beldan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The QMan is not used in FMan IM mode, so no QMI enqueue or QMI
dequeue are performed.
Signed-off-by: Hou Zhiqiang <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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ATM when receiving a packet the whole buffer is invalidated, this change
optimizes this behaviour.
Signed-off-by: Karl Beldan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
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check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.
This gets rid of the remaining warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
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ATM the rx and tx descriptors are handled as cached memory while they
lie in a dedicated RAM of the SoCs, which is an uncached area.
Removing the said dcache ops, while optimizing the logic and clarifying
the code, also gets rid of most of the check_cache_range() incurred
warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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If the functions passed to the registration function are not in the same
C file (extern) then spatch will not handle the dependent changes.
Make those changes manually.
Signed-off-by: Joe Hershberger <[email protected]>
For the 4xx related files:
Acked-by: Stefan Roese <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Some of the changes were a bit too complex.
Signed-off-by: Joe Hershberger <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.
Signed-off-by: Joe Hershberger <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Implement MDIO bus read/write functions, initialize the bus and scan for
the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.
Cc: Michal Simek <[email protected]>
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The ethoc device can be configured to have a private memory region
instead of having access to the main memory. In that case egress packets
must be copied into that memory for transmission and pointers to that
memory need to be passed to net_process_received_packet or returned from
the recv callback.
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Addresses used in buffer descriptors and passed in platform data or
device tree are physical. Addresses used by CPU to access packet data
and registers are virtual. Don't mix these addresses and use virt_to_phys
for translation.
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
device configuration from the device tree.
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Extract reusable parts from ethoc_init, ethoc_set_mac_address,
ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
Add U_BOOT_DRIVER, eth_ops structure and implement required methods.
Signed-off-by: Max Filippov <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Don't use physical base address of registers directly, ioremap it first.
Save pointer in private struct ethoc and use that struct in all internal
functions.
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
only board configuration that uses it and put it into that board's
defconfig.
Cc: Stefan Kristiansson <[email protected]>
Signed-off-by: Max Filippov <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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When adding support for the driver model the SPI EEPROM feature had
been ignored. Fix the build with both CONFIG_DM_ETH and
CONFIG_E1000_SPI enabled.
Signed-off-by: Alban Bedel <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Use the right phy_connect() prototype for CONFIGF_DM_ETH.
Support to get the phy interface from dt and set GMAC_UR.
Signed-off-by: Wenyou Yang <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <[email protected]>
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cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:
CACHE: Misaligned operation at range [dffecec0, dffed016]
Fix it by flushing cache of size aligned to PKTALIGN.
Signed-off-by: Lokesh Vutla <[email protected]>
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Keystone net can have multiple ethernet slaves, currently only
slave 1 is supported by the driver. Register multiple slaves as
individual ethernets to network framework.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Each line should be terminated by semi-colon. It was not caught
earlier as there is a proper statement. Fix it by changing the
comma with semi-colon.
Signed-off-by: Mugunthan V N <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Mugunthan V N <[email protected]>
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This fixes the following CACHE warnings when using sun8i_emac:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)
Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.
Cc: Chen-Yu Tsai <[email protected]>
Cc: Corentin LABBE <[email protected]>
Cc: Amit Singh Tomar <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Acked-by: Ian Campbell <[email protected]>
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This corrects a build error on zynqmp.
Signed-off-by: Simon Glass <[email protected]>
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In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.
It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.
This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.
Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The sun8i_emac driver erroneously configures the AHB2 clock when it
assumes it is configuring the AXI gates, which is not even documented
or ever appeared in either the WiP kernel driver or Allwinner's original
driver.
As a result, AHB2 clock mux is set to an invalid setting, making the
EPHY unusable.
Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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This patch add EMAC driver support for H3/A83T/A64 SoCs.
Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY).
BIG Thanks to Andre for providing some of the DT code.
Signed-off-by: Amit Singh Tomar <[email protected]>
Acked-by: Hans de Goede <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
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If MAC is directly connected to another MAC (like a switch for example)
we don't need to probe for a phy, autoneogation and so on. We simply
have to setup speed.
Signed-off-by: Hannes Schmelzer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <[email protected]>
Cc: Joe Hershberger <[email protected]>
Signed-off-by: Oleksandr Tymoshenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Beniamino Galvani <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Sjoerd Simons <[email protected]>
Cc: Sonic Zhang <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.
Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.
Signed-off-by: Nathan Rossi <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch adds a phy driver for the Micrel KSZ886x switches.
Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.
KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)
This patch supports only unmanaged and MIIM modes.
Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.
Verified with the KSZ8863MLL.
Signed-off-by: Alexey Firago <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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The rtl8169 driver uses a global variable to store the register address
of the adapter being operated upon. This is updated to point at the
correct adapter when sending or receiving a packet, or shutting down the
adapter, but not when initializing the adapter. Consequently, switching
between different adapters within the same U-Boot runtime does not work
correctly since the driver programs the wrong registers during
rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start().
Note that since rtl8169_eth_stop() does set the global variable, the
second consecutive attempt to use the "new" adapter did work even before
this patch, because each time network usage is shut down, the network
core calls stop, which sets the variable so that the next start does
actually initialize the hardware, and the adapter works.
Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so
if using only a single device, or if picking the "right" device (based on
probe order) when multiple devices are present, ioaddr will already be set
correctly from the get-go, so the issue does not occur.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Add driver-model support to this driver. The old code remains for now so
that we can convert boards one at a time.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Adjust this driver to avoid using struct netdev in functions that driver
model will call. Also refactor the receive function to be compatible with
driver model.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: Scott Wood <[email protected]>
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Add ethernet driver for the AR933x and AR934x Atheros MIPS machines.
The driver could be easily extended to other WiSoCs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Wills Wang <[email protected]>
[fixed Kconfig dependency]
Signed-off-by: Daniel Schwierzeck <[email protected]>
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If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.
Signed-off-by: Paul Burton <[email protected]>
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Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.
Signed-off-by: Paul Burton <[email protected]>
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