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path: root/drivers/net
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2019-12-20drivers: net: bcm-sf2: pass -1 to phy_connect()Alex Marginean
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: Alex Marginean <[email protected]> Cc: Jiandong Zheng <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-20net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYsMarek Vasut
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <[email protected]> Cc: Joe Hershberger <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: Ramon Fried <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: ti: am65-cpsw-nuss: Add new compatible for J721eVignesh Raghavendra
Add new compatible to handle J721e SoC Signed-off-by: Vignesh Raghavendra <[email protected]> Acked-by: Joe Hershberger <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
2019-12-09net: ti: am65-cpsw-nuss: Rework RX flow ID handlingVignesh Raghavendra
Get flow ID information for RX DMA channel using dma_get_cfg() interface instead of reading from DT. This is required in order to avoid DT update whenever there is change in the range of flow ID allocated to the host. Signed-off-by: Vignesh Raghavendra <[email protected]> Acked-by: Joe Hershberger <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
2019-12-09net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGNCédric Le Goater
Fixes: e766849713ff ("net: ftgmac100: convert the RX/TX descriptor arrays") Signed-off-by: Cédric Le Goater <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc: register internal MDIO busAlex Marginean
This bus is used to access internal SoC PHYs. These PHYs are configured by the ENETC driver directly, but it's useful to have command line access to this MDIO to debug the system especially when using new external PHYs. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc_mdio: return with time-out if HW is stuckAlex Marginean
On some boards MDIO may get stuck if it detects echo on the line. This is a know hardware issue, there is a board fix for it. In case we're running on a board that doesn't have the fix, we don't want to loop here forever and freeze U-Boot. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc: move PCS and PHY config to probeAlex Marginean
This reduces the time needed to establish a link as we don't reset the link each time the interface is used. Our Link capabilities do not change at run-time so there is no need to re-apply PHY configuration each time. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc: Add 2.5Gbps to supported link speedsAlex Marginean
The original code enabled link speeds up to 1Gbps, but the interface can go up to 2.5G, enable that speed to in PHY AN mask. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc: use the new MDIO DM helper functionsAlex Marginean
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify the code. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: fsl_enetc: use XFI, USXGMII interface type macrosAlex Marginean
Apply 10G PCS init for USXGMII, XFI interface types. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: check system interface too when checking for link upAlex Marginean
In some cases the link on the system interface of the aquantia PHY comes up after the link on line interface. The link state loop only checks the line side, which may result in first packet sent being lost. Use aquantia_link_is_up instead, which checks both system and line side on gen 2/3 PHYs to avoid losing the 1st packet. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: set SMBus addr based on DT propertyAlex Marginean
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses on this interface are normally set up by PHY firmware, but depending on the board they may end up not being unique. Add an optional DT property used to change SMBus address if needed. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: set MDI reversal based on DT propertyAlex Marginean
MDI pins up to the RJ45 connector may be reversed on the board and the default PHY configuration applied by firmware may or may not match that. Add an optional DT property to configure MDI reversal for this case. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: set up SI protocol based on interface typeAlex Marginean
If PHY is not ready for data by the time _config is called, reconfigure the PHY system interface to use the proper protocol based on phydev->interface, just in case the defaults set by PHY firmware don't match current configuration. Signed-off-by: Florin Laurentiu Chiculita <[email protected]> Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: add PHY generation informationAlex Marginean
Uses the data field in phy_driver structure to identify the PHY generation. This is useful for custom configuration as non-generic PHY registers are not 100% compatible between generations. Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09drivers: net: aquantia: use XFI, USXGMII interface typesAlex Marginean
The PHY supports XFI and USXGMII, the notable difference being that USX AN is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and detects whether USX AN should be enabled or not using a PHY status register. Keep that functionality too, so we don't break existing drivers. Signed-off-by: Razvan Ionut Cirjan <[email protected]> Signed-off-by: Alex Marginean <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: fix switch vendor nameAnatolij Gustschin
Fix vendor name in MV88E61xx option description. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Chris Packham <[email protected]> Tested-by: Chris Packham <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: mv88e61xx: register phy_driver struct for 88E6071Anatolij Gustschin
Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Chris Packham <[email protected]> Tested-by: Chris Packham <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071Anatolij Gustschin
On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Chris Packham <[email protected]> Tested-by: Chris Packham <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: mv88e61xx: add CPU port parameter init for 88E6071Anatolij Gustschin
On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Chris Packham <[email protected]> Tested-by: Chris Packham <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: mv88e61xx: rework to enable detection of 88E6071 devicesAnatolij Gustschin
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: micrel: make sure the factory test bit is clearedNicolas Ferre
The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by: Antoine Tenart <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: aquantia: wait for phy init sequence to finishFlorin Chiculita
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by: Florin Chiculita <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: macb: let miiphy_read/_write pass arbitrary addressesJosef Holzmayr
This allows passing arbitrary addresses through macb_miiphy_read and macb_miiphy_write, therefore enabling the mii command to access all mdio bus devices instead of only the defined phy. Signed-off-by: Josef Holzmayr <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: macb: explicitly pass phy_adr to mdio read and writeJosef Holzmayr
To support accessing arbitrary addresses the mii/mdio bus it is necessary that the macb_mdio_read and macb_mdio_write functions do not implicitly use the address of the connected phy. The function signature is extended according to the Linux kernel equivalent. Signed-off-by: Josef Holzmayr <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: Increase link up delay in genphy_update_link()Stefan Roese
I've noticed that in most cases when genphy_update_link() is called, the ethernet driver (mt7628-eth in this case) fails with the first ethernet packets. Resulting in a timeout of the first tftp command. Increasing the delay in the link check look from 1 to 50 ms and moving it below the BMSR register read fixes this issue, resulting in a stable ethernet traffic, even after initial link autonogotiation. Signed-off-by: Stefan Roese <[email protected]> Cc: Weijie Gao <[email protected]> Cc: Joe Hershberger <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: rtl8169: Support RTL-8168c/8111cThierry Reding
This version of the RTL-8168 chip can be found on some add-in cards sold by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it needs to have the ChipCmd register programmed after the DMA descriptors have been set up, so make sure that happens by adding an entry to the chip information table. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: mvpp2: MVPP2 now needs MVMDIONevo Hed
Changes to mvpp2.c require the MVMDIO module which in turn uses DM_MDIO. Signed-off-by: Nevo Hed <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: mvpp2: use new MVMDIO driverNevo Hed
This commit ports mvpp2 to use the recently introduced Marvell MDIO (MVMDIO) driver. It removes direct interaction with the SMI & XSMI busses. This commit is based in part on earlier work by Ken Ma <[email protected]> in Marvell's own downstream repo: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39. The above refrenced work was based on an MVMDIO implementation that never made it into U-Boot. With this patch the mvpp2 driver switches to use the new MVMDIO driver that is based on a more universal mdio-uclass implementation. Signed-off-by: Nevo Hed <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: mvpp2: mark phy as invalid in case of missing appropriate driverGrzegorz Jaszczyk
If the phy doesn't match with any existing u-boot drivers, the phy framework will connect it to the generic one which uid == 0xffffffff. In this case, act as if the phy wouldn't be declared in dts. Otherwise, in case of 3310 (for which the driver doesn't exist) the link is marked as always down. Removing phy entry from dts in case of 3310 is not a good option because it is required for the phy_fw_down procedure. This patch fixes the issue with the link always down on MCBIN board. nhed: added NULL deref test. Signed-off-by: Grzegorz Jaszczyk <[email protected]> Reviewed-by: Igal Liberman <[email protected]> Tested-by: Igal Liberman <[email protected]> Signed-off-by: Nevo Hed <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: mvpp2x: fix traffic stuck after PHY start errorStefan Chulski
Issue: - Network stuck if autonegotion fails. Issue root cause: - When autonegotiation fails during port open procedure, the packet processor configuration does not finish and open procedure exits with error. - However, this doesn't prevent u-boot network framework from calling send and receive procedures. - Using transmit and receive functions of misconfigured packet processor will cause traffic to get stuck. Fix: - Continue packet processor configuration even if autonegotiation fails. Only error message is triggered in this case. - Exit transmit and receive functions if there is no PHY link indication. - U-boot network framework now calls open procedure again during next transmit initiation. Signed-off-by: Stefan Chulski <[email protected]> Reviewed-by: Igal Liberman <[email protected]> Tested-by: Igal Liberman <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: dp83867: refactor rgmii configurationGrygorii Strashko
Refactor SGMII configuration to group all settings together and reduce number of MDIO transactions. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: dp83867: io impedance is not dependent on RGMII delayGrygorii Strashko
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not dependent on RGMII delay") of mainline linux kernel. The driver would only set the IO impedance value when RGMII internal delays were enabled. There is no reason for this. Move the IO impedance block out of the RGMII delay block. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: dp83867: rework delay rgmii delay handlingGrygorii Strashko
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay handling") of mainline linux kernel. The current code is assuming the reset default of the delay control register was to have delay disabled. This is what the datasheet shows as the register's initial value. However, that's not actually true: the default is controlled by the PHY's pin strapping. This patch: - insures the other direction's delay is disabled If the interface mode is selected as RX or TX delay only - validates the delay values and fail if they are not in range - checks if the board is strapped to have a delay and is configured to use "rgmii" mode and warning is generated that "rgmii-id" should have been used. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: dp83867: Add ability to disable output clockGrygorii Strashko
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: dp83867: move static initialization to .probe()Grygorii Strashko
Move static, one-time initialization to .probe() callback. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net: phy: ti: rename ti.c to dp83867.cGrygorii Strashko
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it accordingly. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Joe Hershberger <[email protected]>
2019-12-09net/phy: Fix phy_connect() for phy addr 0Priyanka Jain
Fix 'mask' calculation in phy_connect() for phy addr '0'. 'mask' is getting set to '0xffffffff' for phy addr '0' in phy_connect() whereas expected value is '0'. Signed-off-by: Priyanka Jain <[email protected]> Reported-by: tetsu-aoki via github Acked-by: Joe Hershberger <[email protected]>
2019-12-06Merge tag 'u-boot-rockchip-20191206' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rockchip pwm driver update to support all the SoCs - RK3308 GMAC and pinctrl support - More UART interface support on PX30 and pmugrf reg fix - Fixup on misc for eth_addr/serial# - Other updates on variant SoCs
2019-12-06net: gmac_rockchip: Add support for rk3308David Wu
Add the glue code to allow the rk3308 variant of the Rockchip gmac to provide network functionality. Signed-off-by: David Wu <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2019-12-05Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"Thomas Hebb
Signed-off-by: Thomas Hebb <[email protected]>
2019-12-03net: cpsw: Add NULL pointer checkFaiz Abbas
Add null pointer check to take care of out of memory errors. Signed-off-by: Faiz Abbas <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]>
2019-12-03Convert CONFIG_SYS_CORTINA_FW_IN_MMC et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_CORTINA_FW_IN_MMC CONFIG_SYS_CORTINA_FW_IN_NAND CONFIG_SYS_CORTINA_FW_IN_NOR CONFIG_SYS_CORTINA_FW_IN_REMOTE CONFIG_SYS_CORTINA_FW_IN_SPIFLASH Signed-off-by: Tom Rini <[email protected]>
2019-12-02common: Move command functions out of common.hSimon Glass
Move these functions into the command.h header file which is a better fit. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Daniel Schwierzeck <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2019-12-02common: Move mii_init() function out of common.hSimon Glass
This function belongs in mii.h so move it over. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2019-12-02common: Move get_ticks() function out of common.hSimon Glass
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2019-12-02crc32: Use the crc.h header for crc functionsSimon Glass
Drop inclusion of crc.h in common.h and use the correct header directly instead. With this we can drop the conflicting definition in fw_env.h and rely on the crc.h header, which is already included. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2019-11-17net: gmac_rockchip: add support for px30Heiko Stuebner
Add the glue code to allow the px30 variant of the Rockchip gmac to provide network functionality. Signed-off-by: Heiko Stuebner <[email protected]> Reviewed-by: Kever Yang <[email protected]>
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