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Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256
KiB, total 64 MiB
"Synchronous Abort" handler, esr 0x96000210
elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
x0 : 00000000b79407e8 x1 : 0000000040640000
x2 : 0000000000000050 x3 : 0000000000000000
x4 : 000000000000000a x5 : 0000000000000050
x6 : 0000000000000366 x7 : 00000000b7942308
x8 : 00000000b76407c0 x9 : 0000000000000008
x10: 0000000000000044 x11: 00000000b7634d1c
x12: 000000000000004f x13: 0000000000000044
x14: 00000000b7634d98 x15: 00000000b76407c0
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000b7636dd8 x19: 0000000000000000
x20: 00000000b79407d0 x21: 00000000b79407e8
x22: 0000000040640000 x23: 00000000b7634e58
x24: 0000000000000000 x25: 0000000003800000
x26: 00000000b7bdd000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000b7634d10
Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
Resetting CPU ...
Signed-off-by: Biwen Li <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: Meenakshi Aggarwal <[email protected]>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <[email protected]>
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Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.
Signed-off-by: Meenakshi Aggarwal <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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In case there is an EEPROM attached to the KS8851 MAC and the EEPROM
contains a valid MAC address, the MAC address is loaded into the NIC
registers on power on. Read the MAC address out of the NIC registers
and provide it to U-Boot.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Eugen Hristev <[email protected]>
Cc: Joe Hershberger <[email protected]>
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- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: Razvan Ionut Cirjan <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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- sun8i emac changes (Andre)
- SCP firmware (Samuel)
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This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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When sending a command via the MDIO bus, the Designware MAC expects some
bits in the CMD register to describe the clock divider value between
the main clock and the MDIO clock.
So far we were omitting these bits, resulting in setting "00", which
means "/ 16", so ending up with an MDIO frequency of either 18.75 or
12.5 MHz.
All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek
PHYs seem to be fine with that - although it looks like to be severly
overclocked (the MDIO spec limits the frequency to 2.5 MHz).
However the external 100Mbit PHY on the Pine64 (non-plus) board is
not happy with that, Ethernet was actually never working there, as the
PHY didn't probe.
As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit
SoCs), and use 200 MHz on the H3, we need the highest divider of 128
to let the MDIO clock end up below the required 2.5 MHz.
This enables Ethernet on the Pine64(non-plus).
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The current implementation of sun8i_get_ephy_nodes() makes quite some
assumptions, in general relying on DT path names is a bad idea.
I think the idea of the code was to determine if we are using the
internal PHY, for which there are simpler and more robust methods:
Rewrite (and rename) the existing function to simply lookup the DT node
that "phy-handle" points to, using the device's DT node.
Then check whether the parent of that PHY node is using an "H3 internal
MDIO" compatible string. If we ever get another internal MDIO bus
implementation, we will probably need code adjustments anyway, so this
is good enough for now.
Signed-off-by: Andre Przywara <[email protected]>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The error handling in recv() is somewhat broken, for instance
good_packet isn't really used, and it's hardly readable. Also we try
to check for short or too big packets, but those are actually filtered
out by the hardware.
Simplify the whole routine and improve the error handling:
- Bail out early if the current RX descriptor is not ready.
- Enable propagation of runt, huge and broken packets.
- Check for runt and huge packets, and return 0 to indicate this.
This will force the framework to call free_pkt for cleanup.
- Avoid aligning the packet buffer for invalidation again.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The EMAC soft reset routine was subtly broken, using an open coded
timeout routine without any actual delay.
Remove the unneeded initial reset bit read, and call wait_for_bit_le32()
to handle the timeout correctly.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When iterating over all RX/TX buffers, we were using a rather long "idx"
control variable, which lead to a nasty overlong line.
Replace "idx" with "i" to avoid this.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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To meet the current alignment requirements for our cache maintenance
functions, we were explicitly aligning the *arguments* to those calls.
This is not only ugly to read, but also wrong, as we need to make sure
we are not accidentally stepping on other data.
Provide wrapper functions for the common case of cleaning or
invalidating a descriptor, to make the cache maintenance calls more
readable. This fixes a good deal of the problematic calls.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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There is no reason to invalidate a TX descriptor before we are setting
it up, as we will only write to a field.
Remove the not needed invalidate_dcache_range() call.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When we initialise the TX descriptors, there is no need yet to clean
them all to memory, as they don't contain any data yet. Later we will
touch and clean each descriptor anyway.
However we tell the MAC about the beginning of the chain, so we have to
clean at least the first descriptor, to make it clear that this is empty
and there are no packets to transfer yet.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Before we initialise the RX descriptors, there is no need to *clean*
them from the cache, as we touch them for the first time.
However we should cover the case that those buffers contain dirty cache
lines, which could be evicted and written back to DRAM any time later,
in the worst case *after* the MAC has transferred a packet into them.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The EMAC driver contains a lot of magic bits, although the manuals
and the Linux driver have all names for them.
Define those names and use them when programming the registers.
Also this replaces a lot of readl/mask/writel operations with the much
easier-to-read setbits_le32() macro.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Apparently due to copying from some older or converted driver, the
sun8i_emac driver contains pointless wrapper functions to bridge
between a legacy driver and the driver model.
Since sun8i_emac is (and always was) driver model only, there is no
reason to have those confusing wrappers. Just remove them, and use
the driver model prototypes directly.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When preparing the register value for the MDIO command register, we
start with a zeroed register, so there is no need to mask off certain
bits before setting them.
Simplify the sequence, and rename the variable to a more matching
mii_cmd on the way.
Also the open-coded time-out routine can be replaced with a much safer
and easier-to-read call to wait_for_bit_le32().
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When initialising the TX DMA descriptors, we mostly chain them up,
but of course don't know about any data or its length yet.
That means they are still invalid, and the OWN bit should NOT be set
yet.
In fact when we later tell the MAC about the beginning of the chain,
and enable TX DMA in the start() routine, the MAC will start fetching
TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA
and TX_DMA_CUR_DESC registers.
Clear the owner bit, to not give the MAC the wrong illusion that it
owns the descriptors already.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When phy_startup() returns with an error, because there is no link or
the user interrupted the process, we shall stop the _start() routine
and return with an error, instead of proceeding anyway.
This fixes pointless operations when there is no Ethernet cable
connected, for instance.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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- Octeon TX: Add NAND driver (Suneel)
- Octeon TX: Add NIC driver driver (Suneel)
- Octeon TX2: Add NIC driver driver (Suneel)
- Armada 8040: Add iEi Puzzle-M80 board support (Luka)
- Armada A37xx SPI: Add support for CS-GPIO (George)
- Espressobin: Use Linux model/compatible strings (Andre)
- Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre)
- Armada A37xx: Small cleanup of config header (Pali)
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Set the defaults on probe for the packet buffer size registers
for the i210.
The TX/RX PBSIZE register of the i210 resets to its default value
only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5
chapter 8.3 'Internal Packet Buffer Size Registers'.
If something (another driver, another OS, etc.) modifies this register
from its default value, the e1000 driver doesn't function correctly. It
detects a hang of the transmitter and continuously resets the adapter.
Here we set this value to its default when resetting the i210 to
resolve this issue.
Signed-off-by: Christian Gmeiner <[email protected]>
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Adds support for Network Interface controllers found on
OcteonTX2 SoC platforms.
Signed-off-by: Suneel Garapati <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
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Adds support for Network Interface controllers found on
OcteonTX SoC platforms.
Signed-off-by: Suneel Garapati <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
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The cell_count argument is required when cells_name is NULL.
This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args
This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.
For example:
count = dev_count_phandle_with_args(dev, "array", NULL, 3);
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Bring in the assorted changes that have been staged in the 'next' branch
prior to release.
Signed-off-by: Tom Rini <[email protected]>
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Upon further discussion on the mailing list, we should not get in the
situation where the generic code path to set ethaddr/etc correctly does
not work. Revert this until someone can further debug the smc911x
driver regarding this issue.
This reverts commit 387cbf096e443705fa66776027273ed257ec6ca3.
Signed-off-by: Tom Rini <[email protected]>
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Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: Patrick Delaunay <[email protected]>
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The ethernet controller can read the MAC from EEPROM and display it,
but if ethaddr is not set, the ethernet is still unavailable.
This patch checks will automatically set the MAC address if it has
not already been set.
Signed-off-by: Adam Ford <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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ftgmac100 driver is using hard-coded PHY interface address of zero.
Each board can have different PHY interface address (phy_addr).
This commit modifies the driver to make use of board specific address
by leveraging CONFIG_PHY_ADDR.
Signed-off-by: Thirupathaiah Annapureddy <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
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The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
clock transitions at 1000 Mbps) if delays should be enabled
depending on the interface mode
See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523
So instead of using arbitrary delay values like now, mimic this behaviour.
The behaviour is the same for all of vsc8530/8531/8540/8541 so move that
to a shared function while at it.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.
This follows a similar change introduced into the Linux kernel at
https://lore.kernel.org/netdev/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
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Without DM_ETH, cpsw_priv.dev is an eth_device. Just use its name instead.
Signed-off-by: Sean Anderson <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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Pass a udevice into a few functions so `dev` is defined.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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There's no dev to log with, so pass the device along with the priv data.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvpp2 one of only two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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Remove some prefixes, or get the device from the phy.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvneta is one of two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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No need for indirection here.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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Remove the pdev indirection.
Signed-off-by: Sean Anderson <[email protected]>
Tested-by: Patrick Delaunay <[email protected]>
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The micrel phy driver is already configuring this values from
device tree. So remove the redundant phy configuration call from
this driver.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
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CONFIG_DM_SPI_FLASH is only supported now with passing of driver
conversion deadline from non-DM to DM model. Hence, it's safe to remove
non-DM code check from pfe_spi_flash_init.
Also use CONFIG_ENV_SPI_MODE and CONFIG_ENV_SPI_MAX_HZ instead of
reading reading values from DT.
Signed-off-by: Kuldeep Singh <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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Fix Coverity issue: RESOURCE_LEAK.
leaked_storage: Variable addr going out of scope leaks the storage it
points to.
Fixes: e0152dbed683 ("net: pfe_eth: Use spi_flash_read API to access
flash memory")
Signed-off-by: Kuldeep Singh <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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All the 10G ports that were working in XFI mode were described as
using XGMII (as PHY_INTERFACE_MODE_XFI was not added at the time).
Add the minimal changes required for the FMan code to support XFI.
Signed-off-by: Madalin Bucur <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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PFE DDR addresses are now stored on to a stack varaiable rather
dynamic allocation.
Signed-off-by: Chaitanya Sakinam <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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correction in delay implementation before we exit out of tx timeout.
Signed-off-by: Chaitanya Sakinam <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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