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Different implementation of USER IO register needs different
mapping for bit fields of this register. Add implementation
for this and, since clken is part of USER IO and it needs to
be activated based on per SoC capabilities, add caps in
macb_config where clken specific information needs to be filled.
Signed-off-by: Claudiu Beznea <[email protected]>
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The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
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A sporadic condition occurs when the "bad packet" error is triggered
repeatedly, which results in "bad packet" messages scrolling on the
console during transfer. To avoid triggering this, reset the internal
RXFC count on the first occurance of the "bad packet", which forces
the code to re-read the RX packet count from the MAC, and prevents
any additional "bad packet" messages if there are no more packets in
the MAC. Also print better debug information if this condition occurs.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Eugen Hristev <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Tom Rini <[email protected]>
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Read and retain MAC address across flash and QEMU support.
Signed-off-by: Hongwei Zhang <[email protected]>
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Implement programming MAC address to the hardware also for device model
configuration.
Fixes: b565b18a294f ("board: ge: bx50v3: Enable DM for PCI and ethernet")
Signed-off-by: Ian Ray <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
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Fix typo.
Signed-off-by: Claudiu Beznea <[email protected]>
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Add support for DLL setup on KSZ9131.
Signed-off-by: Claudiu Beznea <[email protected]>
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Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Add a return value to bb_miiphy_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang <[email protected]>
Signed-off-by: Siew Chin Lim <[email protected]>
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Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
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Prepare v2021.01-rc5
Signed-off-by: Tom Rini <[email protected]>
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At present ofnode is present in the device even if it is never used. With
of-platdata this field is not used, so can be removed. In preparation for
this, change the access to go through inline functions.
Signed-off-by: Simon Glass <[email protected]>
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Most drivers use these access methods but a few do not. Update them.
In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: Simon Glass <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>
Acked-by: Pratyush Yadav <[email protected]>
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Checking for seq == -1 is effectively checking that the device is
activated. The new sequence numbers are never -1 for a bound device, so
update the check.
Also drop the note about valid sequence numbers so it is accurate with the
new approach.
Signed-off-by: Simon Glass <[email protected]>
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Several Octeon drivers operate by setting the sequence number of their
device. This should not be needed with the new sequence number setup. Also
it is not permitted. Drop it.
Signed-off-by: Simon Glass <[email protected]>
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At present various drivers etc. access the device's 'seq' member directly.
This makes it harder to change the meaning of that member. Change access
to go through a function instead.
The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now.
Signed-off-by: Simon Glass <[email protected]>
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Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <[email protected]>
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This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.
Signed-off-by: Simon Glass <[email protected]>
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Rename this to be consistent with the change from 'platdata'.
Signed-off-by: Simon Glass <[email protected]>
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We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).
Rename some of the latter variables to end with 'plat' for consistency.
Signed-off-by: Simon Glass <[email protected]>
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This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <[email protected]>
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This function is not needed since the standard device_bind() can be used
instead.
Signed-off-by: Simon Glass <[email protected]>
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This function is not necessary anymore, since device_bind_ofnode() does
the same thing and works with both flattree and livetree.
Rename it to indicate that it is special.
Signed-off-by: Simon Glass <[email protected]>
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Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256
KiB, total 64 MiB
"Synchronous Abort" handler, esr 0x96000210
elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
x0 : 00000000b79407e8 x1 : 0000000040640000
x2 : 0000000000000050 x3 : 0000000000000000
x4 : 000000000000000a x5 : 0000000000000050
x6 : 0000000000000366 x7 : 00000000b7942308
x8 : 00000000b76407c0 x9 : 0000000000000008
x10: 0000000000000044 x11: 00000000b7634d1c
x12: 000000000000004f x13: 0000000000000044
x14: 00000000b7634d98 x15: 00000000b76407c0
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000b7636dd8 x19: 0000000000000000
x20: 00000000b79407d0 x21: 00000000b79407e8
x22: 0000000040640000 x23: 00000000b7634e58
x24: 0000000000000000 x25: 0000000003800000
x26: 00000000b7bdd000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000b7634d10
Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
Resetting CPU ...
Signed-off-by: Biwen Li <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.
Signed-off-by: Meenakshi Aggarwal <[email protected]>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <[email protected]>
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Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.
Signed-off-by: Meenakshi Aggarwal <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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In case there is an EEPROM attached to the KS8851 MAC and the EEPROM
contains a valid MAC address, the MAC address is loaded into the NIC
registers on power on. Read the MAC address out of the NIC registers
and provide it to U-Boot.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Eugen Hristev <[email protected]>
Cc: Joe Hershberger <[email protected]>
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- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.
Signed-off-by: Razvan Ionut Cirjan <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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- sun8i emac changes (Andre)
- SCP firmware (Samuel)
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This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.
Signed-off-by: Robert Marko <[email protected]>
Cc: Luka Perkov <[email protected]>
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When sending a command via the MDIO bus, the Designware MAC expects some
bits in the CMD register to describe the clock divider value between
the main clock and the MDIO clock.
So far we were omitting these bits, resulting in setting "00", which
means "/ 16", so ending up with an MDIO frequency of either 18.75 or
12.5 MHz.
All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek
PHYs seem to be fine with that - although it looks like to be severly
overclocked (the MDIO spec limits the frequency to 2.5 MHz).
However the external 100Mbit PHY on the Pine64 (non-plus) board is
not happy with that, Ethernet was actually never working there, as the
PHY didn't probe.
As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit
SoCs), and use 200 MHz on the H3, we need the highest divider of 128
to let the MDIO clock end up below the required 2.5 MHz.
This enables Ethernet on the Pine64(non-plus).
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The current implementation of sun8i_get_ephy_nodes() makes quite some
assumptions, in general relying on DT path names is a bad idea.
I think the idea of the code was to determine if we are using the
internal PHY, for which there are simpler and more robust methods:
Rewrite (and rename) the existing function to simply lookup the DT node
that "phy-handle" points to, using the device's DT node.
Then check whether the parent of that PHY node is using an "H3 internal
MDIO" compatible string. If we ever get another internal MDIO bus
implementation, we will probably need code adjustments anyway, so this
is good enough for now.
Signed-off-by: Andre Przywara <[email protected]>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The error handling in recv() is somewhat broken, for instance
good_packet isn't really used, and it's hardly readable. Also we try
to check for short or too big packets, but those are actually filtered
out by the hardware.
Simplify the whole routine and improve the error handling:
- Bail out early if the current RX descriptor is not ready.
- Enable propagation of runt, huge and broken packets.
- Check for runt and huge packets, and return 0 to indicate this.
This will force the framework to call free_pkt for cleanup.
- Avoid aligning the packet buffer for invalidation again.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The EMAC soft reset routine was subtly broken, using an open coded
timeout routine without any actual delay.
Remove the unneeded initial reset bit read, and call wait_for_bit_le32()
to handle the timeout correctly.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When iterating over all RX/TX buffers, we were using a rather long "idx"
control variable, which lead to a nasty overlong line.
Replace "idx" with "i" to avoid this.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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To meet the current alignment requirements for our cache maintenance
functions, we were explicitly aligning the *arguments* to those calls.
This is not only ugly to read, but also wrong, as we need to make sure
we are not accidentally stepping on other data.
Provide wrapper functions for the common case of cleaning or
invalidating a descriptor, to make the cache maintenance calls more
readable. This fixes a good deal of the problematic calls.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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There is no reason to invalidate a TX descriptor before we are setting
it up, as we will only write to a field.
Remove the not needed invalidate_dcache_range() call.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When we initialise the TX descriptors, there is no need yet to clean
them all to memory, as they don't contain any data yet. Later we will
touch and clean each descriptor anyway.
However we tell the MAC about the beginning of the chain, so we have to
clean at least the first descriptor, to make it clear that this is empty
and there are no packets to transfer yet.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Before we initialise the RX descriptors, there is no need to *clean*
them from the cache, as we touch them for the first time.
However we should cover the case that those buffers contain dirty cache
lines, which could be evicted and written back to DRAM any time later,
in the worst case *after* the MAC has transferred a packet into them.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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The EMAC driver contains a lot of magic bits, although the manuals
and the Linux driver have all names for them.
Define those names and use them when programming the registers.
Also this replaces a lot of readl/mask/writel operations with the much
easier-to-read setbits_le32() macro.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Apparently due to copying from some older or converted driver, the
sun8i_emac driver contains pointless wrapper functions to bridge
between a legacy driver and the driver model.
Since sun8i_emac is (and always was) driver model only, there is no
reason to have those confusing wrappers. Just remove them, and use
the driver model prototypes directly.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When preparing the register value for the MDIO command register, we
start with a zeroed register, so there is no need to mask off certain
bits before setting them.
Simplify the sequence, and rename the variable to a more matching
mii_cmd on the way.
Also the open-coded time-out routine can be replaced with a much safer
and easier-to-read call to wait_for_bit_le32().
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When initialising the TX DMA descriptors, we mostly chain them up,
but of course don't know about any data or its length yet.
That means they are still invalid, and the OWN bit should NOT be set
yet.
In fact when we later tell the MAC about the beginning of the chain,
and enable TX DMA in the start() routine, the MAC will start fetching
TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA
and TX_DMA_CUR_DESC registers.
Clear the owner bit, to not give the MAC the wrong illusion that it
owns the descriptors already.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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When phy_startup() returns with an error, because there is no link or
the user interrupted the process, we shall stop the _start() routine
and return with an error, instead of proceeding anyway.
This fixes pointless operations when there is no Ethernet cable
connected, for instance.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Tested-by: Amit Singh Tomar <[email protected]> # Pine64+
Reviewed-by: Jagan Teki <[email protected]>
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Necessary for dev_xxx.
Signed-off-by: Sean Anderson <[email protected]>
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- Octeon TX: Add NAND driver (Suneel)
- Octeon TX: Add NIC driver driver (Suneel)
- Octeon TX2: Add NIC driver driver (Suneel)
- Armada 8040: Add iEi Puzzle-M80 board support (Luka)
- Armada A37xx SPI: Add support for CS-GPIO (George)
- Espressobin: Use Linux model/compatible strings (Andre)
- Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre)
- Armada A37xx: Small cleanup of config header (Pali)
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Set the defaults on probe for the packet buffer size registers
for the i210.
The TX/RX PBSIZE register of the i210 resets to its default value
only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5
chapter 8.3 'Internal Packet Buffer Size Registers'.
If something (another driver, another OS, etc.) modifies this register
from its default value, the e1000 driver doesn't function correctly. It
detects a hang of the transmitter and continuously resets the adapter.
Here we set this value to its default when resetting the i210 to
resolve this issue.
Signed-off-by: Christian Gmeiner <[email protected]>
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