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The COMA, ETHA, GWCA offsets differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize these offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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This IP does support operating MII and SerDes via different ports.
Currently, the driver assumes that MII and SerDes are always bound
together on the same port, but this may not be the case. Implement
support for controlling MII and SerDes separately.
While the change is extensive, the gist of the change is to pass
pointer to the selected port registers to MII or SerDes functions,
depending on which port and operations should be done on that port.
Each combined ETHA instance contains both MII and SerDes register
pointers, which may not point to the same port, and passes those
registers to MII and SerDes functions respectively to control the
MII or SerDes of each port.
Signed-off-by: Marek Vasut <[email protected]>
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The new version of RSwitch3 in Renesas R-Car Gen5 uses multiple
clock to supply the IP. Convert the driver to bulk clock API to
cater for both single clock of R-Car S4 and multiple clock of
R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Empty RX DMA descriptor must contain .die_dt field set to DT_FEMPTY,
because hardware DMA overwrites this field to non-DT_FEMPTY when data
are received, and the .recv callback tests the content of RX descriptor
.die_dt field to determine whether hardware did receive any data and
updated the .die_dt field, and based on that information, receives a
packet or not. Fix the incorrect RX DMA descriptor initialization to
assure the .recv callback always works correctly.
Signed-off-by: Marek Vasut <[email protected]>
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Remove macros which are not used in the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Fix indent from multiple spaces to tabs, to be consistent with
coding style and the rest of the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Add support for the optional 'phy-supply' property in the ENETC MDIO
driver. This allows the driver to enable and manage the PHY's power
supply via the regulator framework when specified in device tree.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
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Extend the NETC block control driver to support the i.MX94 SoC.
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
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A device-tree property is already defined to indicate that the internal
PHY should be used with active-low leds, which corresponds to a
specific bit in the dedicated syscon register.
Add support for setting this bit when the property is present.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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We know about all the relevant fields in the syscon register so there
is no reason to read it first and modify it.
Build the register from scratch instead, with all relevant fields set.
Signed-off-by: Paul Kocialkowski <[email protected]>
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The Synchronous Abort and reset errors occurred due
to incorrect parameter passing during initialization.
Signed-off-by: Jim Liu <[email protected]>
[jf: add missing #if IS_ENABLED(CONFIG_BITBANGMII)]
Signed-off-by: Jerome Forissier <[email protected]>
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With commit 597fe041a85f ("net/phy: enable get_phy_id redefinable") we
made get_phy_id a public but weak function, so that PHY drivers that had
required non-standard ways of getting the PHY ID could be supported.
However, overloading a weak function multiple times is (rightly) a link
error. At this point, we have two PHYs which make use of this feature,
so make both of them only available when COMPILE_TEST is unset, as part
of being able to support "allyesconfig" in the future.
Signed-off-by: Tom Rini <[email protected]>
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Synchronize paged PHY helpers with Linux v6.17.
Add support for PHY devices that use paged register access by
implementing the following functions:
- phy_save_page(): Save current page number
- phy_select_page(): Switch to a specific page and return previous page
- phy_restore_page(): Restore previously saved page
Also adds read_page and write_page callbacks to the phy_driver
structure to enable driver-specific page handling.
These helpers allow safe access to paged PHY registers by ensuring
proper page selection and restoration,
even in error conditions, which will be used by the Airoha PHY driver.
Signed-off-by: Lucien.Jheng <[email protected]>
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The commit 997786bbf473 ("drivers/net/airoha_eth: fix stalling in package
receiving") can be improved. Instead of returning previous descriptor
it's possible:
* do nothing in even descriptor case
* return 2 descriptor to the queue (current and previous) in the odd
descriptor case.
This patch:
* implements above approach
* remove logic not required within new approach
* adds note that PKTBUFSRX must be even and larger than 7
for reliable driver operations
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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In preparation for support of MDIO on AN7581, move the MT7531 MMIO logic
to a dedicated driver and permit usage of the mdio read/write function
to the mtk_eth driver.
This only affect MT7988 that can use MMIO operation to access the Switch
register. The MT7988 code is updated to make use of the external driver.
This permits Airoha driver to make use of DM_MDIO to bind for the MT7531
driver that have the same exact register.
Signed-off-by: Christian Marangi <[email protected]>
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Correctly free the MDIO Bus on calling cleanup function. While at it
also fix a copy-paste error and rename the cleanup function name to the
more specific name.
Signed-off-by: Christian Marangi <[email protected]>
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On exiting the phy_setting function for MT7988, the PHY page is never
restored to Page 0. This can cause all kind of problem with reading the
status of the PHY at runtime.
Correctly restore PHY page on exiting the PHY setting function.
Signed-off-by: Christian Marangi <[email protected]>
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The PHY for MT7531/MT7988 are never actully turned ON/OFF for the
affected PHY as we are read/writing to the wrong PHY address.
This is caused by the fact that we use the MT753X_PHY_ADDR macro 2
times offsetting the address multiple times.
One in the _setup() function and one in the mt7531_mii_read/write.
Drop the additional usage of MT753X_PHY_ADDR in setup() to correctly
set the PHY.
Signed-off-by: Christian Marangi <[email protected]>
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Use PHY API phy_get_ofnode() helper to get PHY DT node.
Signed-off-by: Beiyan Yun <[email protected]>
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In this case, the mediatek network drivers cannot build outside of
ARCH_MEDIATEK or ARCH_MTMIPS, and so express this requirement in Kconfig
as well. In the case of DWC_ETH_XGMAC / DWC_ETH_XGMAC_SOCFPGA, the file
controlled by the DWC_ETH_XGMAC option references a socfpga-specific
array defined in the file controlled by DWC_ETH_XGMAC_SOCFPGA. Rework
these options in Kconfig to handle this dependency.
Signed-off-by: Tom Rini <[email protected]>
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Some drivers which depend on SoCFPGA specific headers had not had
appropriate dependencies list in Kconfig. Add ARCH_SOCFPGA or
TARGET_SOCFPGA_SOC64 where appropriate.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2
zynqmp:
- DT updates
- Enable new commands
mbv:
- Simplify defconfigs
clk:
- Separate legacy handler and use SMC handler
misc:
- Tighten TTC Kconfig dependency
net:
- Add 10GBE support to Gem
pwm:
- cadence-ttc: Fix array sizes
fwu:
- Add platform hook support
spi:
- Remove undocumented cdns,is-dma property
video:
- Fix DPSUB RGB handling
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The am65-cpsw driver currently sets the SEL_RGMII_IDMODE flag in a MAC's
mode register to enable or disable the TX delay. While this was supported
for earlier generations of the CPSW controller, the datasheets of all
modern TI SoCs using the am65-cpsw MAC state that the TX delay is fixed,
and the SEL_RGMII_IDMODE bit is documented as reserved in most of them.
Furthermore, while it was found that this bit does in fact disable the TX
delay, [1] states that this setting is truly unsupported by TI and not
just undocumented.
Following the clarification of the rgmii* phy-mode values in the Linux
DT bindings in [2], the Linux am65-cpsw driver was changed in [3] to
account for the fixed TX delay by fixing up the mode passed to the PHY
driver; a similar fixup already existed in the TI icssg-prueth driver.
[4] followed up on this by explicitly clearing the SEL_RGMII_IDMODE flag
to handle the case where it is set by the bootloader or other firmware
before Linux.
With the above changes, Device Trees that set the recommended "rgmii-id"
mode are now appearing in Linux 6.17+. Avoid setting the unsupported
SEL_RGMII_IDMODE flag for such Device Trees, and instead fix up the PHY
interface mode, thus aligning the U-Boot driver with the Linux kernel.
[1] https://www.spinics.net/lists/netdev/msg1112647.html
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c360eb0c3ccb95306704fd221442283ee82f1f58
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca13b249f291f4920466638d1adbfb3f9c8db6e9
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a22d3b0d49d411e64ed07e30c2095035ecb30ed2
Signed-off-by: Matthias Schiffer <[email protected]>
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The script based firmware loader does not use anything from the
fs_loader implementation. Separate it into its own library source
file and convert the mediatek PHY to use this separate code. This
should reduce the amount of code that is pulled in alongside the
firmware loader, as the FS loader is no longer included.
Signed-off-by: Marek Vasut <[email protected]>
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Add 10GBE high-speed Mac support, it supports 10G, 5G, 2.5G and 1G speeds.
10GBE high speed Mac is an extension of the current 1G Mac in versal,
inheriting all its current features.
MMI 10GBE ip has two internal PCS's.
1)10GBASER PCS is used for higher speeds 10G and 5G.
2)1000BASEX PCS is used for slower speeds 1G and 2.5G.
Both PCS's speed and rate configuration is done with same
usx registers. ENABLE_HS_MAC bit in NCR is the toggle switch
between the PCS's.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Use plain buffer pointer in request_firmware_into_buf_via_script()
instead of a pointer to pointer. The later is not necessary as the
request_firmware_into_buf_via_script() does not modify the buffer
pointer. Update the mediatek driver to match.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Weijie Gao <[email protected]>
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Merge the outstanding changes from the 'next' branch to master.
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This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.
Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.
The vendor SDK sets this bit along with the PHY_ID bits.
Ported from the Linux change at [1] from Da Xu merged in
commit [2].
[1] https://lore.kernel.org/all/[email protected]/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")
Suggested-by: Da Xue <[email protected]>
Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org
Signed-off-by: Neil Armstrong <[email protected]>
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Use regulator_set_enable_if_allowed() to avoid failure if regulator is
shared between multiple devices.
Signed-off-by: Ben Wolsieffer <[email protected]>
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Replace MII with RMII as it is a Reduced Media-Independent Interface.
Signed-off-by: Yegor Yefremov <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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Prepare v2025.10-rc5
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ethernet PHY (v4)"
Weijie Gao <[email protected]> says:
This patch adds PHY driver for MediaTek MT7987/MT7988 built-in 2.5Gb
ethernet PHY.
[trini: Change 'tristate' Kconfig to 'bool']
Link: https://lore.kernel.org/r/[email protected]
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The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Associate PHY device with its device node specified by phy-handle
property. This makes it possible for PHY drivers to read dedicated
information to configure the PHY device.
Signed-off-by: Weijie Gao <[email protected]>
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Greg Malysa <[email protected]> says:
Between 2025.07 and 2025.10 many header dependency chains were improved,
but this exposed implicit header usage in several of our drivers. This
wasn't discovered before or included in the original fixes because our
drivers are not yet used by any mainline-supported boards, so build
tests did not find them. This series addresses the two build failures
I've encountered while rebasing our work onto 2025.10 and continuing to
prepare the next submission of our board files.
Link: https://lore.kernel.org/r/[email protected]
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Following header dependency cleanups, an implicit dependence on env.h
was exposed in dwc_eth_qos_adi. However because this driver is not (yet)
enabled in any defconfigs, build tests did not identify the missing
header. This adds the missing #include so that the driver builds
correctly when enabled.
Signed-off-by: Greg Malysa <[email protected]>
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The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.
Fixes: 20afca89ed53 ("net: dwc_eth_qos: add support of stm32mp2 platform")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Christophe ROULLIER<[email protected]>
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Prepare v2025.10-rc4
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Add a MAINTAINERS entry for the DesignWare XGMAC network driver to
ensure future patches are properly routed for review and support.
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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In mc_fixup_dpc_mac_addr noff is assigned the return value from
fdt_add_subnode so that is the variable that should be passed to
fdt_strerror and returned when negative.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In dpni_exit there is a NULL check for dflt_dpni after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpni after free in both dpni_init
and dpni_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In dpbp_exit there is a NULL check for dflt_dpbp after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpbp after free in both dpbp_init
and dpbp_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In dpio_exit there is a NULL check for dflt_dpio but it happens after
dpio_dflt has been dereferenced a number of times already. Instead move
the NULL check to first thing in the function. Also assign NULL to
dflt_dpio after free in both dpio_init and dpio_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In netc_blk_ctrl_probe the test for failure of the function
clk_prepare_enable should not return PTR_ERR(ipg_clk) as it does not
check IS_ERR(ipg_clk) instead it should return err as that is what is
holding the error code in this case.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In memac_wait_until_free and memac_wait_until_done the use of
post-decrement on the test in the while loop for a timeout means that
timeout will be equal to -1 on exit in that case. Adjust the test for
this expected value.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In fm_eth_bind there is a dereference of dev before it is NULL checked.
Add a NULL check before the first dereference and remove a later NULL
check that is now redundant.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In bmi_rx_port_disable and bmi_tx_port_disable the use of post-decrement
on the test in the while loop for a timeout means that timeout will be
equal to -1 on exit in that case. Adjust the test for this expected
value.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Prepare v2025.10-rc3
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The timeout test in axi_dma_init is not correct due to the
post-decrement used on the timeout variable which will mean timeout is
not 0 if the timeout occurs. Make the timeout variable an int instead of
a u32 and then test for timeout being -1.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Chintan Vankar <[email protected]> says:
This series adds bind method for CPSW to avoid explicit probing, removes
explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
SK-AM62P-LP, J722S, SK-AM69.
Link: https://lore.kernel.org/r/[email protected]
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