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Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng <[email protected]>
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The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
[bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c]
Signed-off-by: Bin Meng <[email protected]>
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This parameter is needed by the PCI driver-mode interface but is always
NULL on x86. There are a number of calls to this function so it makes
sense to minimise the parameters.
Adjust the x86 function to omit the first parameter, and introduce stub
functions to handle the conversion.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <[email protected]>
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At present this hedaer is only available on x86. To allow sandbox to use
it for testing, move it to a common location.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present this fails silently which can be confusing since some devices
on the PCI bus may not work correctly. Show a message in this case.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: add a '\n' in the PCI autoconfig fail message]
Signed-off-by: Bin Meng <[email protected]>
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If PCI auto-config runs out of memory, show a few more details to help
diagnose the problem.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
[bmeng: change %x to %llx to avoid build warnings on some platforms]
Signed-off-by: Bin Meng <[email protected]>
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At present U-Boot runs autoconfig in SPL but this is best left to U-Boot
proper. For TPL and SPL we can normally used fixed BARs and save code size
and time.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Update the debugging info a little to show the result of trying to bind
a PCI device.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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At present PCI emulation devices are not probed before use, since they
used to be children of the device that used them, and children cannot be
probed before their parents.
Now that PCI emulation devices are attached to the root node, we can
simply probe them, and avoid using the internal function.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng <[email protected]>
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Sandbox pci works using emulation drivers which are currently children of
the pci device:
pci-controller {
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
emul@1f,0 {
compatible = "sandbox,swap-case";
};
};
};
In this case the emulation device is attached to pci device on address
f800 (device 1f, function 0) and provides the swap-case functionality.
However this is not ideal, since every device on a PCI bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.
Worse, child devices cannot be probed before their parents. This forces
us to use 'find' rather than 'get' to obtain the emulator device. In fact
the emulator devices are never probed. There is code in
sandbox_pci_emul_post_probe() which tries to track when emulators are
active, but at present this does not work.
A better approach seems to be to add a separate node elsewhere in the
device tree, an 'emulation parent'. This could be given a bogus address
(such as -1) to hide the emulators away from the 'pci' command, but it
seems better to keep it at the root node to avoid such hacks.
Then we can use a phandle to point from the device to the correct
emulator, and only on sandbox. The code to find an emulator does not
interfere with normal pci operation.
Add a new UCLASS_PCI_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. Update the existing
device trees and the code for finding an emulator.
This brings PCI emulators more into line with I2C.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
[bmeng: fix 3 typos in the commit message;
encode bus number in the labels of swap_case_emul nodes;
mention commit 4345998ae9df in sandbox_pci_get_emul()]
Signed-off-by: Bin Meng <[email protected]>
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Many support functions are common between FSP1 and FSP2. Add a new header
to handle this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
[bmeng: remove forward declarations in fsp_support.h]
Signed-off-by: Bin Meng <[email protected]>
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Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.
Add a Kconfig which defines which version is in use.
Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Tested-by: Bin Meng <[email protected]>
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Convert the SH7751 PCI driver to DM and add DT probing.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Bin Meng <[email protected]>
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Add compatible string for MPC8548 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for P5040 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for P4080 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for P3041 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for P2041 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for PCIe of P1020, P1021, P1024, P1025
and P2020 SoCs.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for T104x PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for T102x PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add compatible string for T4240 PCIe.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe240000) and stride (0x10000)
to calculate the controller's index.
Fix it by adding the related info to the driver data
structure.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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The Class Code fixup method was changed from PCIe block
revision 3.0, the current fixup is only valid for the
revision 3.0 and the later ones.
So add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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This can avoid build error:
The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only
defined on the platforms that select the CONFIG_FOO, while
it's not defined on platforms that do not select the
CONFIG_FOO.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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- Various improvements to Keymile boards - mostly DT conversation
(Pascal & Holger)
- Removal of now unsupported Keymile boards (Pascal & Holger)
- Small MVEBU PCI fix (Marek)
- Turris Omnia defconfig update (Marek)
- Misc Allied Telesis defconfig updates (Chris)
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- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
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Add driver supporting PCIe root-complex available
on TI's AM65x SoC.
Signed-off-by: Sekhar Nori <[email protected]>
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The non-DM version of this driver used to set BAR0 register after the
calls to pci_set_region.
I found out that for some strange reason the ath10k driver in kernel
fails to work if this is done the other way around.
I know that Linux's driver should not depend on how U-Boot does things,
but for some strange reason it does and this seems to be the simplest
solution. Fix it since it caused regressions on Omnia.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Dirk Eibach <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Chris Packham <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: VlaoMao <[email protected]>
Tested-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Move env_get() over to the new header file.
Acked-by: Joe Hershberger <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This fix issue when access config from PCIe switch.
The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.
The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.
Signed-off-by: Ley Foon Tan <[email protected]>
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Hardware return completion status non-zero when read from non exist
function in multi-function PCIe device. Return error will cause PCIe
enumeration fail.
Change it to return 0 and return value 0xffffffff when error.
Signed-off-by: Ley Foon Tan <[email protected]>
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Some PCIe devices require longer time to response.
Increase polling counter to 20000 (~100ms).
Signed-off-by: Ley Foon Tan <[email protected]>
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Use the uclass_first_device_check and uclass_next_device_check functions
instead of uclass_first_device and uclass_next_device in pci_init. This
ensures that all PCI devices are tried to be probed. Currently if a
device fails to probe, the enumeration stops and the devices which come
after the failed device are not probed.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Anton Schubert <[email protected]>
Cc: Dirk Eibach <[email protected]>
Cc: Mario Six <[email protected]>
Cc: Chris Packham <[email protected]>
Cc: Phil Sutter <[email protected]>
Cc: VlaoMao <[email protected]>
Cc: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function,
if FLR is supported.
Signed-off-by: Alex Marginean <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Makes dm_pci_map_bar API available for integrated PCI devices that
support Enhanced Allocation instead of the original PCI BAR mechanism.
Signed-off-by: Alex Marginean <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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commit b7598a43f2b4 ("[PATCH] Avoid assigning PCI resources from
zero address") only moved the bus lower address to 0x1000 if the
given bus start address is zero. The comment said 0x1000 is a
reasonable starting value, hence we'd better apply the same
adjustment when the given bus start address is below 0x1000.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add PCIe DM driver for Freescale PowerPC PCIe controllers.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add DM support and support for probing the iMX PCI driver from DT.
The legacy non-DM support is retained, however shall be removed once
DM PCI is the only option remaining.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Pass the driver private data around the driver as much as possible, instead
of having it as a static global variable. This is done in preparation for
the DM conversion, no functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Pull out hard-coded register base addresses into driver private
structure in preparation for DM conversion. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
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Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Bao Xiaowei <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Prabhakar Kushwaha <[email protected]>
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Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs.
The PCIe on Gen3 is used both to connect external PCIe peripherals.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
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vme8349.h contains two separate boards: The vme8349 itself, and the
caddy2 board. The caddy2 board is chosen by setting certain config
variables. Create a proper config file for the caddy2 board to make
Kconfig migration easier.
Furthermore, simplify the vme8349 and caddy2 configs by keeping only the
options necessary for each board.
Signed-off-by: Mario Six <[email protected]>
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CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace
CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349.
Signed-off-by: Mario Six <[email protected]>
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Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options.
Signed-off-by: Mario Six <[email protected]>
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When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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