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MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.
Signed-off-by: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Cc: [email protected]
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This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.
Signed-off-by: Minghuan Lian <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Increase size PCI memory mapping from 32MiB to 128MiB.
Signed-off-by: VlaoMao <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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We have at least a minor count of boards, that failed to re-initialize
PCI express in the Linux kernel. Typical failure rate is 20% on affected
boards. This is mitigated by commit 6ecbe1375671 ("drivers: pci: imx:
add imx_pcie_remove function").
However, at least on some i.MX6 custom boards, when calling
assert_core_reset() as part of the first-time PCIe init, read access
to PCIE_PL_PFLR simply hangs. Surround this readl() with
imx_pcie_fix_dabt_handler() does not help. For this reason, the forced
LTSSM detection is only used on the second assert_core_reset() that is
called shorly before starting the Linux kernel.
Signed-off-by: Sven-Ola Tuecke <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Tested-by: David Müller <[email protected]>
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QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Use the new helpers to avoid boilerplate in the driver.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Use the new helper function to avoid boilerplate in the driver.
Note that this changes __raw_writel et al. to writel. AFAICT this is
no problem because:
- The Linux driver for the same hardware uses the non-__raw variants as
well (via pci_generic_config_write()).
- This driver seems to be used only on MIPS so far, where the __raw and
non-__raw accessors are the same.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This sort of pattern for implementing memory-mapped PCI config space
accesses appears in U-Boot twice already, and a third user is coming up.
So add helper functions to avoid code duplication, similar to how Linux
has pci_generic_config_write and pci_generic_config_read.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <[email protected]>
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Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.
Signed-off-by: Bharat Bhushan <[email protected]>
Signed-off-by: Ioana Ciornei <[email protected]>
[YS: revised commit message]
Reviewed-by: York Sun <[email protected]>
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'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This field has never been used as the driver has been DM-based since the
beginning. Drop it.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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These take the 'struct udevice *' as an argument, not the
'struct xilinx_pcie *` which is a local variable. Fix the comments to
match the code.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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With DM video, this is not used any more. Drop it.
Signed-off-by: Bin Meng <[email protected]>
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We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: Hou Zhiqiang <[email protected]>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h
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Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914
Signed-off-by: Santan Kumar <[email protected]>
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Update the tegra pci driver to support a live device tree. Fix the check
for nvidia,num-lanes so that an error will actually be detected.
Tested-by: Marcel Ziswiler <[email protected]>
Tested-on: Beaver, Jetson-TK1
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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This function returns the pointer to the value of a node property.
The current name ofnode_read_prop() is confusing. Follow the naming
of_get_property() from Linux.
The return type (const u32 *) is wrong. DT property values can be
strings as well as integers. This is why of_get_property/fdt_getprop
returns an opaque pointer.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The of_n_addr_cells() and of_n_size_cells() functions are useful for
getting the size of addresses in a node, but in a few places U-Boot needs
to obtain the actual property value for a node without walking up the
stack. Add functions for this and just the existing code to use it.
Add a comment to the existing ofnode functions which do not do the right
thing with a flat tree.
This fixes a problem reading PCI addresses.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
Tested-on: Beaver, Jetson-TK1
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There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
include/configs/imx6qdl_icore_rqs.h
include/configs/imx6ul_geam.h
include/configs/imx6ul_isiot.h
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There was for long time no activity in the 8260 area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8260,
so remove it.
Signed-off-by: Heiko Schocher <[email protected]>
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The declarations should not be in common.h. Move them to the arch-specific
headers.
Signed-off-by: Simon Glass <[email protected]>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <[email protected]>
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Update the PCI uclass to support livetree. This mostly involves fixing
the address decoding from the device tree.
Signed-off-by: Simon Glass <[email protected]>
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These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.
In the end we will have:
1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only
All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.
Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: Simon Glass <[email protected]>
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There is no dedicated reset signal wired up for the MX6QDL thus if the
bootloader enables the link we need some special handling to get the core
back into a state where it is safe to touch it for configuration.
While there has been some special handling in the Linux kernel to do this,
it was removed in 4.11 thus we need to do it properly in the bootloader
and therefore without this if you enable PCI in the bootloader you will hang
while booting the 4.11 kernel.
This puts the PCIe controller back into a safe state for the kernel driver
before launching the kernel.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Peter Senna Tschudin <[email protected]>
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The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Santan Kumar <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can
bypass executing VGA roms in S3.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Stefan Roese <[email protected]>
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strdup uses malloc to allocate memory for str.
If we cannot bind to the generic driver we should release
the memory.
The problem was indicated by clang scan-build.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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This patch allows probing all PCIe nodes defined in DTS
even if there no device connected to such node (no link).
Without this fix the driver returns -ENODEV when the PCIe
link is down. As result the pci_init function stops
scanning bus on first empty PCIe slot and all devices
located in higher numbered buses are not discovered.
Signed-off-by: Konstantin Porotchkin <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Nadav Haklai <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.
Signed-off-by: Bharat Bhushan <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.
Signed-off-by: Bharat Bhushan <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Minghuan Lian <[email protected]>
Reviewed-by: York Sun <[email protected]>
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In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.
Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y
Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin <[email protected]>
Signed-off-by: Rabeeh Khoury <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Neta Zur Hershkovits <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Haim Boot <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <[email protected]>
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This is not supported, so disable it for now.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Armada 38x has four PCI ports, not three.
The optimization in pci_init_board() seems to assume that every port has
three lanes. This is obviously wrong, and breaks support for Armada 38x.
Signed-off-by: Dirk Eibach <[email protected]>
Signed-off-by: Mario Six <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This is not used in U-Boot. Drop this option and associated dead code.
Signed-off-by: Simon Glass <[email protected]>
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The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers. This should be done
immediately after resetting the PCI Express controller.
Reviewed-by: Hamish Martin <[email protected]>
Signed-off-by: Tony O'Brien <[email protected]>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <[email protected]>
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