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Enable full rate divider configuration support for J721E_WIZ_16G for SGMII.
Signed-off-by: Siddharth Vadapalli <[email protected]>
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Select the same mac divider for SGMII too as the one being used for
QSGMII.
Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.
Signed-off-by: Siddharth Vadapalli <[email protected]>
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Add support for j721s2-wiz-10g device to use clock-names interface
instead of explicitly defining clock nodes within device tree node.
Signed-off-by: Ravi Gunasekaran <[email protected]>
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The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Signed-off-by: Sinthu Raja <[email protected]>
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It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.
Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.
Signed-off-by: Sinthu Raja <[email protected]>
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Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.
Signed-off-by: Matt Ranostay <[email protected]>
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Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.
Based on: https://lore.kernel.org/linux-phy/[email protected]/T/#u
Cc: Roger Quadros <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
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Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju <[email protected]>
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Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.
This is an adaptation of the linux driver.
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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