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path: root/drivers/phy
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2021-10-25phy: sun4i-usb: Support VBUS detection via power supplySamuel Holland
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2021-10-25phy: sun4i-usb: Refactor VBUS detection to match LinuxSamuel Holland
The Linux driver checks the VBUS detection GPIO first; then VBUS power supply; then finally assumes VBUS is present. When adding VBUS power supply support, we want to match that order, so we get the same behavior in case both a GPIO and a power supply are provided in the device tree. So refactor the function a bit to remove the early return, and use the same "assume VBUS is present" final fallback. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2021-10-25phy: sun4i-usb: Remove a couple of debug messagesSamuel Holland
Both of these messages log the GPIO number of the ID detection GPIO, which is not terribly useful, especially in the VBUS detection function. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2021-10-12Merge tag 'u-boot-stm32-20211012' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - Disable ATAGS for STM32 MCU and MPU boards - Disable bi_boot_params for STM32 MCU and MPU boards - Update stm32-usbphyc node management - Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards - Convert some USB config flags to Kconfig for various boards - Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board - Remove specific CONFIG_STV0991 flags - Remove unused CONFIG_USER_LOWLEVEL_INIT flag - Add ofdata_to_platdata() callback for stm32_spi driver - Update for stm32f7_i2c driver - Remove gpio_hog_probe_all() from STM32 MP1 board - Fix bind command Signed-off-by: Tom Rini <[email protected]>
2021-10-08phy: marvell: a3700: Return correct error code when power up failsPali Rohár
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-10-08phy: marvell: a3700: Fix configuring polarity invert bitsPali Rohár
phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406 Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-10-08phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initializationPali Rohár
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-10-08phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-nodePatrick Delaunay
Add protection on presence and order of the phy node sub node by using the mandatory reg information. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-10-08phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphycPatrick Delaunay
The vbus-supply is an optional property of sub-node connector node. and no more in the usb phyc node (in first proposed binding). This regulator for USB VBUS may be needed for host mode. See the latest kernel binding for details in Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml. usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; }; }; Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk
Signed-off-by: Wolfgang Denk <[email protected]>
2021-09-27Merge tag 'v2021.10-rc5' into nextTom Rini
Prepare v2021.10-rc5
2021-09-27phy: marvell: cp110: Support SATA invert polarityDenis Odintsov
In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <[email protected]> Cc: Baruch Siach <[email protected]> Cc: Rabeeh Khoury <[email protected]> Cc: Stefan Roese <[email protected]> Reviewed-by: Stefan Roese <[email protected]>
2021-09-22phy: sun50i-usb3: Add a driver for the H6 USB3 PHYSamuel Holland
This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <[email protected]> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <[email protected]>
2021-07-29Merge tag 'ti-v2021.10-rc2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-ti - Add MMC High speed modes for AM64 and J7200 - Add Sierra/Torrent SERDES driver - Minor clean-ups for R5F boot from SPL
2021-07-28Makefile: Move phy rules into drivers/phySimon Glass
These don't belong in the drivers Makefile so move them down into the correct place. Signed-off-by: Simon Glass <[email protected]> [trini: Fixup some missing dependencies this exposed] Signed-off-by: Tom Rini <[email protected]>
2021-07-27phy: meson-axg-mipi: Access parent ofnode through dev_ofnode()Alper Nebi Yasak
With commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private") and commit f10643cf8a4c ("dm: core: Access device ofnode through functions") accesses to the "node" member were replaced with dev_ofnode(). Also apply that replacement here. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Signed-off-by: Alper Nebi Yasak <[email protected]> Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2021-07-27phy: meson-axg-mipi: Rename "priv_auto_alloc_size" to "priv_auto"Alper Nebi Yasak
With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". Apply the rename to these two drivers as well. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Fixes: 7ef19503bacf ("phy: Add Amlogic AXG MIPI D-PHY driver") Signed-off-by: Alper Nebi Yasak <[email protected]> Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27phy: cadence: Add driver for Torrent SERDESAswath Govindraju
Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Alan Douglas <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQYe Li
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <[email protected]> Reviewed-by: Patrick Wildt <[email protected]> Tested-by: Patrick Wildt <[email protected]>
2021-07-14phy: Add driver for ST-Ericsson AB8500 USB PHYStephan Gerhold
The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2021-07-14phy: socionext: Add UniPhier PCIe PHY driverKunihiko Hayashi
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]>
2021-07-10phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSBPaul Kocialkowski
Recent Allwinner platforms (starting with the H3) only use the MUSB controller for peripheral mode and use HCI for host mode. As a result, extra steps need to be taken to properly route USB signals to one or the other. More precisely, the following is required: * Routing the pins to either HCI/MUSB (controlled by PHY); * Enabling USB PHY passby in HCI mode (controlled by PMU). The current code will enable passby for each PHY and reroute PHY0 to MUSB, which is inconsistent and results in broken USB peripheral support. Passby on PHY0 must only be enabled when we want to use HCI. Since host/device mode detection is not available from the PHY code and because U-Boot does not support changing the mode dynamically anyway, we can just mux the controller to MUSB if it is enabled and mux it to HCI otherwise. This fixes USB peripheral support for platforms with PHY0 dual-route, especially H3/H5 and V3s. Signed-off-by: Paul Kocialkowski <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2021-04-29phy: marvell: utmi: update utmi config which fixes usb2.0 instabilityGrzegorz Jaszczyk
- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: add support for SFI1Igal Liberman
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <[email protected]> Signed-off-by: Konstantin Porotchkin <[email protected]>
2021-04-29phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: allow to initialize up to 6 USB portsGrzegorz Jaszczyk
New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Reviewed-by: Kostya Porotchkin <[email protected]>
2021-04-29phy: marvell: cp110: mark u-boot power-off callsIgal Liberman
It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by: Igal Liberman <[email protected]> Reviewed-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: fix handling of unconnected comphyChristine Gharzuzi
- the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by: Christine Gharzuzi <[email protected]> Signed-off-by: Igal Liberman <[email protected]> Reviewed-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: pass sgmii id to firmwareIgal Liberman
Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware. Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38 Signed-off-by: Igal Liberman <[email protected]> Reviewed-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: cp110: clean up driver after it was moved to atfGrzegorz Jaszczyk
Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Reviewed-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: remove both phy and pipe selector configurationGrzegorz Jaszczyk
Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode. Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Reviewed-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: let the firmware perform training for XFIGrzegorz Jaszczyk
Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Signed-off-by: Stefan Roese <[email protected]> Reviewed-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for USBGrzegorz Jaszczyk
Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e Signed-off-by: Grzegorz Jaszczyk <[email protected]>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for RXAUIGrzegorz Jaszczyk
Replace the comphy initialization for RXAUI with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Reviewed-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: remove unused definitionsMarcin Wojtas
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <[email protected]> Signed-off-by: Konstantin Porotchkin <[email protected]>
2021-04-29phy: marvell: enable comphy info prints for all devicesIgal Liberman
Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743 Signed-off-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: add RX training commandIgal Liberman
This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman <[email protected]> Signed-off-by: Marcin Wojtas <[email protected]>
2021-04-29phy: marvell: save comphy_map_data priv structureIgal Liberman
This allows the lower level driver access to comphy map data (required for RX training support, which is introduced in the following patches). Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa Signed-off-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: fix several minor bugs in comphy_probeIgal Liberman
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID Move the error print if phy-type is invalid Add continue to the probe loop (in a case of invalid phy) Cosmetic changes Change-Id: I0c61b40bfe685437426fe907942ed338b7845378 Signed-off-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: utmi: update analog parameters according to latest ETPIgal Liberman
Add UTMI analog parameters initialization values according to latest ETP. Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8 Signed-off-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: cp110: initialize only enabled UTMI unitsOmri Itach
UTMI should be initialized only for enabled device tree nodes. This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled. This way the internal configuration structure will only contain valid ports information obtained from the DT. Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8 Signed-off-by: Omri Itach <[email protected]> Signed-off-by: Ken Ma <[email protected]>
2021-04-29phy: marvell: add missing speed during info printsIgal Liberman
In get_speed_string() we have an array (speed_strings[]) which includes all possible speed strings. This array size and content must be aligned to the speed defines in comphy_data.h. This patch adds missing 5.125G speed, aligns speed_strings[] and fixes incorrect printing when speed > 5.0G. Change-Id: I9900d23595094be321be0c62fcaa88036324568e Signed-off-by: Igal Liberman <[email protected]>
2021-04-29phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <[email protected]> Signed-off-by: Konstantin Porotchkin <[email protected]>
2021-04-29phy: marvell: add comphy type PHY_TYPE_USB3jinghua
- For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by: jinghua <[email protected]> Signed-off-by: Ken Ma <[email protected]> Reviewed-by: Igal Liberman <[email protected]>
2021-04-19phy: meson-g12a-usb3-pcie: add support for PCIe opsNeil Armstrong
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver. Signed-off-by: Neil Armstrong <[email protected]>
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