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https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next
* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro
* MT8189 clock qualifier fix
* Phase-aware PSCI reset (MT8195/MT8365)
* dwc_eth_qos MT8366 support
* MediaTek TPHY v3 hardware support
* mtk_snor mt8188/mt8189 compatible-string cleanup
* MT6358/MT6366 PMIC regulator + pwrap support
* MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*)
* New MT8366 pinctrl driver + dt-bindings header
* MediaTek serial driver clock-handling fixes
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Add driver containing pinctrl register maps for MT8366.
Signed-off-by: Deep Pani <[email protected]>
Signed-off-by: Macpaul Lin <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Change the MediaTek pinctrl Kconfig to just have a single option for
all targets. This will simplify adding new targets and SPL support in
the future.
There is only one MediaTek target that does not have a pinctrl driver.
All other targets enable it by default so the configs don't have to
explicitly set it in addition to just enabling PINCTRL.
In the Makefile, we can use the target config symbol to automatically
select the correct driver. And the config selector on the common file
was redundant since we already have the same in the parent Makefile,
so it is dropped. Targets are also sorted while we are touching this.
Suggested-by: Quentin Schulz <[email protected]>
Closes: https://lore.kernel.org/u-boot/[email protected]/
Acked-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-3-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Remove #if conditionals that checked if PINCONF was enabled. The Kconfig
now selects PINCONF, so it will always be enabled and we don't need the
checks anymore.
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-2-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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All MediaTek targets include pinconf registers so we should just always
select PINCONF instead of requiring each config to explicitly enable it.
MT8518 was the only target that didn't have PINCONF already enabled in
the defconfig, so it will be enabled there by default now. (This was
likely unintentional as the MT8518 driver does define pinconf registers
for drive and pull so supports pinconf operations.)
Link: https://patch.msgid.link/20260807-mtk-pinctrl-kconfig-cleanup-v2-1-509a8f833181@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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The code was synced with linux-pinctrl/for-next (future linux-7.3) branch.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Tested-by: Daniel Schwierzeck <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-snapdragon into next
* Support for building mbn files during the build with the new mkmbn
tool.
* Remove UCLASS_SMEM and the old smem driver (Qualcomm was the only
user of both), replace it with a port of the Linux SMEM driver.
* Refactor memory map parsing and support reading the memory layout from
the SMEM database.
* Set the serial# from SMEM.
* Introduce initial support for SPL in mach-snapdragon.
* Add a defconfig for sm8650 with U-Boot as the primary bootloader.
* Workaround an MMC issue by limiting the transfer size.
* Add support for SM7125/SC7180 (clock/pinctrl drivers and UFS phy).
* Add support for the QCS6490 powered Rubik Pi 3 board and document it.
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This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP. Add support for SC7180 pinctrl block.
Signed-off-by: Vitalii Skorkin <[email protected]>
Signed-off-by: Erikas Bitovtas <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU and TPU
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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Reduce the PFC tables further by gating DRIF, MLB, TMU, TPU and SATA
behind PINCTRL_PFC_FULL, none of which are currently supported by
U-Boot. This helps reduce the size of the bootloader in 4 kiB range.
Signed-off-by: Marek Vasut <[email protected]>
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A bunch of code calls info->dev, mostly dev_* messages and devm_kzalloc.
The former can be passed a NULL device and _dev_printk handles this just
fine.
The latter ignores the dev argument whenever !CONFIG_IS_ENABLED(DEVRES)
which was true in most cases until we made CONFIG_DEVRES mandatory for
U-Boot proper in commit 217cf656e249 ("dm: core: Default to using DEVRES
outside of xPL"). Failing to set info->dev before it's used by
devm_kzalloc results in crashes, therefore let's set info->dev before it
can be used.
Reported-by: Ben Schneider <[email protected]>
Closes: https://lore.kernel.org/u-boot/IRefanijM8fTzOXeGe-H5hmhRkm7pt4Q83BV6VcWKlWp0s4i8mYcONTQz-IVhvNWlGta4LtnfK7ti6gxlrqq8h8cotgG1S0Fs6_DviAHvyo=@bens.haus/
Fixes: 0871806629b5 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Fixes: 217cf656e249 ("dm: core: Default to using DEVRES outside of xPL")
Signed-off-by: Quentin Schulz <[email protected]>
Tested-by: Ben Schneider <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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single_add_gpio_func() calls ofnode_parse_phandle_with_args() once per
gpio-range entry. With a flat device tree, every call re-iterates the
property from index 0 and, because cellname is set, performs an
fdt_node_offset_by_phandle() (a full-FDT scan) at every step. The total
cost is therefore quadratic in the number of entries and proportional to
the size of the device tree.
The impact depends on when the pinctrl is probed. On the J722S EVM
defconfig, pinctrl@f4000 (main_pmx0, the SoC's stock 7-entry gpio-range)
is probed after relocation (caches on): single_add_gpio_func() takes
~18 ms there and ~1 ms with this change. When the node is probed before
relocation (caches off) the same parse takes hundreds of ms; on a board
that probes it pre-relocation and runs LPDDR4 clocked down it reached
723 ms, cut to 22 ms here. Any pinctrl-single user with a populated
gpio-range property pays this cost.
The phandle target is never dereferenced by this function (only the
argument cells are stored), so resolve it only for the first entry to
learn the per-entry cell count, then read the argument cells directly
with ofnode_read_u32_index() and allocate the ranges in one block. A
zero phandle still terminates the list, as in the original loop. This
follows the existing pinctrl-single,gpio-range usage observed in current
DTs, where entries use the same provider and therefore a uniform
per-entry cell count.
Signed-off-by: Jordi Trepat Mur <[email protected]>
Reviewed-by: Anshul Dalal <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-sunxi
Beside a fix for a long standing bug in the A80 eMMC code, this adds
SPI booting support for the Allwinner A523/A527/T527 class of boards.
The second major feature is support for the secondary Ethernet controller
on that same SoC. This might not be as important as for the kernel (I
doubt that U-Boot acts as a router), but for once some boards only connect
the secondary EMAC, and on others people might have the boot server only
reachable via this port.
There are some smaller fixes and improvements still queued up, but they
need some more testing and are minor, so can land a bit later.
The world build timed out, but the rest passed, and I booted that briefly
on an A523 board with two Ethernet ports.
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https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip
- Switched to use upstream pinctrl header include,
- Dropped SDHCI DT properties in U-Boot-specific DT for NanoPi R5 as
most are present upstream and those which aren't are breaking devices,
- Fixed ECC strength mismatch between reading and writing on non-0
NAND chips configured as boot medium (nand-is-boot-medium),
- Moved Simon to reviewer for ARM ROCKCHIP,
- Fixed build issue related to GPT capsule support accessing a struct
member only present when CONFIG_PARTITION_TYPE_GUID is set,
- Added support for new devices:
- Anbernic RG-DS
- ROC-RK3588S-PC
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The Allwinner sun55i (A523/A527/T527) platform provide a Synopsys
DesignWare Ethernet QOS IP block as the gmac1 controller, which uses
pins PJ0 to PJ16. Add the gmac1 function to the pinctrl driver to
support it.
Signed-off-by: Junhui Liu <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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The use of RK_GPIOn defines is deprecated in the upstream
rockchip.h file. Replace all them by the gpio number.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
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The use of RK_FUNC_n defines is deprecated in the upstream
rockchip.h file. Replace all them by the function number.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Quentin Schulz <[email protected]>
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Add pinctrl driver for Spacemit K1 SoC.
Signed-off-by: Raymond Mao <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
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Billy Tsai <[email protected]> says:
The AST2700 is Aspeed's 7th-generation BMC SoC with a dual-die
architecture: SoC0 (CPU die) and SoC1 (I/O die) each have their own SCU
with independent multi-function pin controls. Initial AST2700 platform
support is already merged in next, including the ast2700.dtsi pinctrl0
and pinctrl1 nodes, but no pinctrl driver backs them yet.
This series adds one pinctrl driver per die, each followed by a patch
adding its pin configuration support. Both drivers use the generic
pinctrl framework and are compatible with the Linux kernel device tree
bindings, using the same group and function names as the Linux
aspeed,ast2700-soc0/soc1-pinctrl drivers so pin states can be shared
between the kernel and U-Boot device trees.
Patch 1 adds the SoC0 driver, which models each (function, group) pair
as a flat register mask/value table covering eMMC, VB, VGA DDC, JTAG
master port select, PCIe RC PERST and USB2/USB3 port routing. Patch 2
adds SoC0 pin configuration support: every GPIO18A/GPIO18B ball has
its own IO control register providing a 3 mA to 41 mA drive strength
selector and bias control.
Patch 3 adds the SoC1 driver, porting the per-pin 4-bit multi-function
selector scheme (220 pins, 238 groups, 217 functions) together with
the virtual pins for PCIe RC2 PERST, the USB2 port C/D mode and SGMII
controls. Patch 4 adds SoC1 pin configuration support: a per-pin bias
enable bit and sparse 2-bit drive strength fields (4 mA to 16 mA in
4 mA steps) mirroring the Linux driver layout.
The bias-disable, bias-pull-down, bias-pull-up and drive-strength
properties can be applied per pin or per group. Both drivers implement
gpio_request_enable so the GPIO driver can reclaim pins through the
gpio-ranges already present in ast2700.dtsi, and provide
get_pin_muxing so "pinmux status" reports the active signal of every
pin.
Link: https://lore.kernel.org/r/[email protected]
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The SoC1 SCU provides a bias enable bit per pin in the registers at
0x480 (setting the bit disables the bias; the pull direction is fixed
in silicon) and 2-bit drive strength fields at 0x4C0 selecting 4 mA to
16 mA in 4 mA steps. The pin-to-field mapping of the drive strength
registers is sparse and non-linear, so it is kept in a lookup table
mirroring the Linux driver; pins without an entry reject
drive-strength with -ENOTSUPP.
Support the bias-disable, bias-pull-down, bias-pull-up and
drive-strength properties per pin and per group, and select PINCONF so
the generic pinctrl framework parses them.
Signed-off-by: Billy Tsai <[email protected]>
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Add the pinctrl driver for the AST2700 SoC1 (I/O) die.
Unlike previous Aspeed generations, the SoC1 SCU assigns every pin a
4-bit multi-function selector field in a contiguous register range
starting at SCU 0x400, eight pins per register. Only bits [2:0] of
each field select the function; bit 3 is reserved read-only and must
not be written. The driver therefore keeps per-pin group tables and
per-function mux values, mirroring the Linux
aspeed,ast2700-soc1-pinctrl driver, and shares the same device tree
bindings: 220 pins, 238 groups and 217 functions with identical names,
so pin states written for the Linux driver work unmodified.
A few controls live outside the pin-indexed range and are handled as
virtual pins: PCIERC2_PERST (SCU 0x908), the USB2 port C/D mode fields
(SCU 0x3B0) and SGMII0 (SCU 0x47C).
The gpio_request_enable hook restores a pin to GPIO by writing mux
value 0, except for the ADC-capable balls W17..AB19 where function 1
selects GPIO and 0 selects the ADC input.
Signed-off-by: Billy Tsai <[email protected]>
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Each GPIO18A/GPIO18B ball has its own IO control register starting at
SCU 0x480, providing a 4-bit drive strength selector (3 mA to 41 mA in
hardware-defined steps), a bias enable bit and a pull direction bit.
Extend the group table with the pin members of the ball-backed groups
so bias-disable, bias-pull-down, bias-pull-up and drive-strength
properties can be applied per group as well as per pin. The routing
groups (USB, JTAG, PCIe RC) have no package balls and reject pin
configuration with -ENOTSUPP.
Select PINCONF so the generic pinctrl framework parses the pin
configuration properties.
Signed-off-by: Billy Tsai <[email protected]>
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The AST2700 is a dual-die BMC SoC: SoC0 (CPU die) and SoC1 (I/O die)
each have their own SCU with independent multi-function pin controls.
Add the pinctrl driver for the SoC0 die. The driver uses the generic
pinctrl framework and is compatible with the Linux kernel device tree
bindings, i.e. pin states are described with the same "function" and
"groups" properties and the same names as the Linux
aspeed,ast2700-soc0-pinctrl driver.
Unlike the older AST2500/AST2600 SCUs where each signal is enabled by
independent bits, the SoC0 mux selections mix single-bit enables
(eMMC, VGA DDC, VB strap), multi-bit selector fields (JTAG master port
select, USB2/USB3 port routing) and reset-control bits (PCIe RC
PERST). Model each (function, group) pair as one register
mask/value write so all of them fit a single flat table.
The gpio_request_enable hook releases the GPIO18A/GPIO18B pins to GPIO
mode by clearing every signal enable bit that claims the pin, matching
the Linux driver behaviour.
Signed-off-by: Billy Tsai <[email protected]>
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This patch adds U-Boot pin controller and gpio driver for Airoha EN7523 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch adds U-Boot pin controller and gpio driver for Airoha AN7583 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch adds U-Boot pin controller and gpio driver for Airoha AN7581 SoC.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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This patch introduce shared Airoha pinctrl code.
Also it sorts contents of pinctrl makefile.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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sorting rules:
* rules for generic pinctrl files placed first,
* obj-y rules,
* obj-$(CONFIG_ARCH_something) rules
* obj-$(CONFIG_PINCTRL_something) rules
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: David Lechner <[email protected]>
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Restyle all Kconfigs for "pinctrl":
Menu entries : no space left
Menu attributes: 1 TAB
Help text : 1 TAB + 2 spaces
Replace '---help---' by 'help'
Signed-off-by: Johan Jonker <[email protected]>
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Replace snprintf() with scnprintf() in the MediaTek pinctrl driver.
snprintf() returns the number of characters that _would_ have been
written if the buffer were large enough, while scnprintf() returns the
number of characters actually written to the buffer. Since we use the
return value to advance the buffer pointer, we need to use scnprintf()
to have the correct pointer arithmetic.
Fixes: 76da7482cf39 ("pinctrl: mediatek: print bias info along with pinmux")
Reviewed-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260506-mtk-pinctrl-fix-scnprintf-v1-1-56b99d5809db@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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These assorted patch series from Peng Fan (OSS) <[email protected]>
have the goal to remove the direct usage of devfdt_ APIs in drivers. The
device APIs supports both live device tree and flat DT backends,
avoiding direct dependency on devfdt_* helpers.
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Use dev_read_addr() which supports both live device tree and flat DT
backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
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Use dev_read_addr_index() which supports both live device tree and flat
DT backends, avoiding direct dependency on devfdt_* helpers.
No functional changes.
Signed-off-by: Peng Fan <[email protected]>
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Prepare v2026.07-rc3
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Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6125 SoC, with support for special pins.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
soc98: input: 1 [x] [email protected]
soc98: input: 0 [x] [email protected]
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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After discussion with the devicetree maintainers we agreed to not extend
lists with the generic compatible "apple,pinctrl" anymore [1]. Use
"apple,t8103-pinctrl" as fallback compatible as it is the SoC driver and
bindings were originally written for.
The t602x (M2 Pro/Max/Ultra) devicetrees submitted in [2] use this
compatible as fallback instead of "apple,t8103-pinctrl".
Link: https://lore.kernel.org/asahi/[email protected]/ [1]
Link: https://lore.kernel.org/asahi/[email protected]/ [2]
Signed-off-by: Janne Grunau <[email protected]>
Acked-by: Mark Kettenis <[email protected]>
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Boards based on the Allwinner D1/T113-s3, such as the
NetCube Systems Nagami, can expose a third I2C controller
on PG10/PG11. However, the sun20i_d1 pinctrl function table
lacked an entry for this mux.
Add the "i2c3" function with mux value 3 on PG10/PG11, allowing device
trees to enable the I2C3 controller.
Signed-off-by: Lukas Schmid <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on Milos SoC, with support for special pins.
Correct pin configuration is required for working debug UART and eMMC/SD
cards.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added pingrp support to sc7280 pinctrl driver based on the
similar U-Boot and Linux drivers.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This patch fixes mt7981 pin register offsets and field definitions.
Signed-off-by: Weijie Gao <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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In the original code, I wrote a custom pin muxing parser but the
upstream device trees wouldn't accept something like that so it would
have complicated mergine the device tree files.
Use the standard device tree format with function and groups:
pinmux1: pinmux1 {
function = "f_gpio1";
groups = "grp_1", "grp_3";
};
Signed-off-by: Dan Carpenter <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-mediatek
This is the first wave of MediaTek changes for this merge window. We
also expect to be sending another decent-sized pull request later for
the backlog of patches that are currently waiting on dependencies or
need little more time for review.
* Fixes for cargo-culted issues in mach-mediatek init.c files.
* Some consistency cleanups of recently added Genio boards (510/700/1200).
* Some pinctrl improvements to support newer MediaTek SOCs (mt8189 compatible).
* New devicetree and config for Genio 520/720 EVK boards (can boot to eMMC or SD).
* New CPU-specific functions to read vendor-specific CPU info at runtime.
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The U_BOOT_DRIVER macro creates a list of drivers used at link time, and
all entries here must be unique. This in turn means that all entries in
the code should also be unique in order to not lead to build failures
later with unexpected build combinations. Typically, the problem we have
here is when a driver is obviously based on another driver and didn't
update this particular field and so while the name field reflects
something unique the linker entry itself is not. In a few places this
provides a more suitable string name as well, however.
Reviewed-by: Marek Vasut <[email protected]>
Reviewed-by: Svyatoslav Ryhel <[email protected]> # Tegra
Reviewed-by: Peter Robinson <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Set the get_pinconf functions for the mt8189 pinctrl driver. This will
append pinconf bias info to the output of the pinmux status command.
This is useful for debugging pin configuration issues.
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add functionality to be able to print pin bias settings along with the
pinmux setting.
This can be useful to debug why pins might not be working correctly.
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Fix setting pinconf bias for MT8189.
Using mtk_pinconf_bias_set_v1() was wrong because MT8189 does not have
PULLEN/PULLSEL registers. It has PU and PD registers for most pins.
MSDC pins need special handling since they have PUPD/R1/R0 registers.
I2C pins need special handling since they have PU/PD/RSEL registers.
New groups are added for MSDC and I2C pins and the bias_set callback
is now set appropriately for all groups.
A new table is needed for the RSEL registers since those were missing.
Some new macros are introduced to avoid repeating the same info many
times in MTK_TYPED_PIN(). This also fixes the semantically incorrect
use of DRV_GRPX for the IO_TYPE_GRPX field.
Reviewed-by: Macpaul Lin <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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Add a new PINCTRL_PIN_REG_RSEL register type and a new function
mtk_pinconf_bias_set_pu_pd_rsel() to handle setting it.
Some MediaTek SoCs have a pin configuration register called RSEL that
sets the resistance value for bias pullup/pulldown.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: David Lechner <[email protected]>
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