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Add a pin controller driver for Meson GXBB adapted from Linux kernel.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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'-' is never used in function names.
Signed-off-by: Masahiro Yamada <[email protected]>
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AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers. In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.
Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed. The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.
Signed-off-by: Simon Glass <[email protected]>
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This new function is more convenient for callers, and handles pre-relocation
situations automatically.
Signed-off-by: Simon Glass <[email protected]>
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Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Andreas Färber <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The rk3288 pinctrl is very specific to this soc, so should
not hog the generic rockchip naming.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This does not have much impact on behavior, but makes code look more
more like Linux. The use of devm_ioremap() often helps to delete
.remove callbacks entirely.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add support for of-platdata with rk3288. This requires disabling access to
the device tree and renaming the driver to match the string that of-platdata
will search for.
Signed-off-by: Simon Glass <[email protected]>
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Signed-off-by: Masahiro Yamada <[email protected]>
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SPL does not use all of the devices, so we can save some memory
footprint.
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]
Signed-off-by: Masahiro Yamada <[email protected]>
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PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Signed-off-by: Masahiro Yamada <[email protected]>
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Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Signed-off-by: Masahiro Yamada <[email protected]>
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This SoC does not support NAND CS1. This place-holder is no longer
necessary.
Signed-off-by: Masahiro Yamada <[email protected]>
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My mistake in the initial support patch.
Signed-off-by: Masahiro Yamada <[email protected]>
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These are pin group names, not function names.
Signed-off-by: Masahiro Yamada <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
configs/peach-pi_defconfig
configs/peach-pit_defconfig
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The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size
of the cell array to accomedate that, otherwise only the first 10 get
configured.
Signed-off-by: Sjoerd Simons <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.
The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.
Cc: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Minkyu Kang <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Minkyu Kang <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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It is possible to have multiple pin controllers in the system. Use the
DM_UC_FLAG_SEQ_ALIAS flag so that the pinctrl instances are assigned
a sequence number.
Cc: Masahiro Yamada <[email protected]>
Cc: Simon Glass <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by: Wills Wang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck <[email protected]>
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This is a simple pinctrl driver, it just support uart and spi pin-mux now.
Signed-off-by: Wills Wang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck <[email protected]>
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I found many mistakes in the initial version.
Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver")
Signed-off-by: Masahiro Yamada <[email protected]>
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Make function/array names match the file names for consistency.
Signed-off-by: Masahiro Yamada <[email protected]>
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The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.
Signed-off-by: Masahiro Yamada <[email protected]>
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Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.
Signed-off-by: Masahiro Yamada <[email protected]>
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Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin. (While, existing ones only support it
per pin-group.) This commit prepares the core part for that.
Signed-off-by: Masahiro Yamada <[email protected]>
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The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens
because pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones. Having flags would be better than
adding new members every time a new SoC-specific capability comes up.
At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Signed-off-by: Masahiro Yamada <[email protected]>
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Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <[email protected]>
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The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long. It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family. Also, rename files for consistency.
Signed-off-by: Masahiro Yamada <[email protected]>
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CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER
to guard the drivers/pinctrl/uniphier directory.
The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it
into CONFIG_PINCTRL_UNIPHIER.
Signed-off-by: Masahiro Yamada <[email protected]>
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While IECTRL is disabled, input signals are pulled-down internally.
If pin-muxing is set up first, glitch signals (Low to High transition)
might be input to hardware blocks.
Bad case scenario:
[1] The hardware block is already running before pinctrl is handled.
(the reset is de-asserted by default or by a firmware, for example)
[2] The pin-muxing is set up. The input signals to hardware block
are pulled-down by the chip-internal biasing.
[3] The pins are input-enabled. The signals from the board reach the
hardware block.
Actually, one invalid character is input to the UART blocks for such
SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
power on reset.
To avoid such problems, pins should be input-enabled before muxing.
[ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ]
Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support")
Signed-off-by: Masahiro Yamada <[email protected]>
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Introudce i.MX7 pinctrl driver support.
For now only i.MX7D supported.
There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr.
To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg
and conf_reg can begin at 0.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
pinctrl-names = "default";
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
>;
};
[.....]
};
there is no property named function or groups. So pinctrl_generic_set_state
can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
"
set_state_simple op missing
imx_pinctrl_set_state: i2c1grp
mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x14c val 0x10
select_input: offset 0x5d8 val 0x1
write config: offset 0x3bc val 0x7f
mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x148 val 0x10
select_input: offset 0x5d4 val 0x1
write config: offset 0x3b8 val 0x7f
"
this means imx6 pinctrl driver works as expected.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus
require no muxing.
Signed-off-by: Purna Chandra Mandal <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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BUILD_BUG_* macros have been defined in several headers. It would
be nice to collect them in include/linux/bug.h like Linux.
This commit is cherry-picking useful macros from include/linux/bug.h
of Linux 4.4.
I did not import BUILD_BUG_ON_MSG() because it would not work if it
is used with include/common.h in U-Boot. I'd like to postpone it
until the root cause (the "error()" macro in include/common.h causes
the name conflict with "__attribute__((error()))") is fixed.
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.
Signed-off-by: Simon Glass <[email protected]>
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Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.
Signed-off-by: Simon Glass <[email protected]>
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This file has many features that are not needed by SPL. Use #ifdef to
remove the unused features and reduce the code size.
Signed-off-by: Simon Glass <[email protected]>
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GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.
Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.
Signed-off-by: Simon Glass <[email protected]>
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We can make use of the device tree to configure pinctrl settings. Add this
support for the driver so we can use it in U-Boot proper.
Signed-off-by: Simon Glass <[email protected]>
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This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.
Adjust it, adding an enum to improve readability.
Signed-off-by: Simon Glass <[email protected]>
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Add a function which produces a flags word from a few common PIN_CONFIG
settings. This is useful for simple pinctrl drivers that don't need to worry
about drive strength, etc.
Signed-off-by: Simon Glass <[email protected]>
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Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding.
Signed-off-by: Jeffy Chen <[email protected]>
Acked-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This can create a large number of pinctrl devices. It chews up early
malloc() memory and takes time. Only bind those which are marked as needed
before relocation.
Signed-off-by: Simon Glass <[email protected]>
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Add a driver which support pin multiplexing setup for rk3036
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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