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This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present
Signed-off-by: Simon Glass <[email protected]>
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To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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GPIO management is pretty simple and is part of the same IP than the pin
controller for the Armada 37xx SoCs. This patch adds the GPIO support to
the pinctrl-armada-37xx.c file, it also allows sharing common functions
between the gpio and the pinctrl drivers.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Ported to U-Boot based on the Linux version by Stefan Roese.
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Konstantin Porotchkin <[email protected]>
Cc: Nadav Haklai <[email protected]>
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Each time set_state is called, a new piece memory will
be allocated for pin_data, but not freed, this will
incur memory leak.
When error, the devm API could not free memory automatically.
So need call devm_kfree when error.
Issue reported by Coverity
Signed-off-by: Peng Fan <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Agner <[email protected]>
Cc: Stefano Babic <[email protected]>
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Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.
Signed-off-by: James Balean <[email protected]>
Cc: Felix Brack <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Felix Brack <[email protected]>
Tested-by: Felix Brack <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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To add HDMI support for the RK3399, this commit provides the needed
pinctrl functionality to configure the HDMI I2C pins (used for reading
the screen's EDID).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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GMAC controller need to init the tx io driver strength to 13mA,
just like the description in dts pinctrl node, or else the controller
may only work in 100MHz Mode, and fail to work at 1000MHz mode.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected] <mailto:[email protected]>>
Reviewed-by: Simon Glass <[email protected]>
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This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <[email protected]>
Tested-by: Jakob Unterwurzacher <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
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With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds gpio driver supporting driver model for stm32f7 gpio.
Signed-off-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Christophe KERELLO <[email protected]>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <[email protected]>
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This originally started out as
"pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.
However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).
Signed-off-by: Philipp Tomsich <[email protected]>
Acked-by: Simon Glass <[email protected]>
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AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The config options for pinctrl on the RK3188, RK3288, RK3328 and
RK3399 previously showed up in menuconfig with the generic string
descriptor "Rockchip pin control driver" requiring one to look through
the help/full description to identify which chip each menu entry was
for.
This change renames each option with the chip-name in the description
string to make it easy to identify the configuration options in
menuconfig.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
include/configs/colibri_vf.h
include/configs/pcm052.h
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This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
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This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.
Signed-off-by: Vikas Manocha <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add i.MX7ULP pinctrl driver.
Select CONFIG_PINCTRL_IMX7ULP to use this driver.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by : Stefano Babic <[email protected]>
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Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Kever Yang <[email protected]>
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Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.
So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.
The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Kever Yang <[email protected]>
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Do not use the API which of-platdata not support.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Added rockchip tag:
Signed-off-by: Simon Glass <[email protected]>
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rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Added rockchip tag:
Signed-off-by: Simon Glass <[email protected]>
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Add STMicroelectronics STiH410 pinctrl driver
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Support the following DT properties:
"bias-disable"
"bias-pull-up"
"bias-pull-down"
"bias-pull-pin-default"
"input-enable"
"input-disable"
My main motivation is to support pull up/down biasing. For Pro5 and
later SoCs, the pupdctrl register number is the same as the pinmux
number, so this feature can be supported without having big pin
tables.
Signed-off-by: Masahiro Yamada <[email protected]>
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <[email protected]>
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Add pin configuration and pinmux support for UniPhier PXs3 SoC.
Signed-off-by: Masahiro Yamada <[email protected]>
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Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins.
Fixes: fc9da85c6059 ("pinctrl: uniphier: add Ethernet pin-mux settings")
Signed-off-by: Masahiro Yamada <[email protected]>
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Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn <[email protected]>
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There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
is for IOMUXC_SNVS.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.
Signed-off-by: Konstantin Porotchkin <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Nadav Haklai <[email protected]>
Cc: Neta Zur Hershkovits <[email protected]>
Cc: Omri Itach <[email protected]>
Cc: Igal Liberman <[email protected]>
Cc: Haim Boot <[email protected]>
Cc: Hanna Hawa <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist
functions") broke codying style in some places especially
by inserting an extra whitespace before fdt_stringlist_count().
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Marek reports warnings in UniPhier pinctrl drivers when compiled by
GCC 6.x, like:
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c:58:18: warning:
'usb3_muxvals' defined but not used [-Wunused-const-variable=]
static const int usb3_muxvals[] = {0, 0};
^~~~~~~~~~~~
My intention here is to compile minimum set of pin data for SPL to
save memory footprint, but GCC these days is clever enough to notice
unused data arrays.
We can fix it by sprinkling around __maybe_unused on those arrays,
but I did not do that because they are counterparts of the pinctrl
drivers in Linux. All the pin data were just copy-pasted from Linux
and are kept in sync for maintainability.
I chose a bit tricky way to fix the issue; calculate ARRAY_SIZE of
*_pins and *_muxvals and set their sum to an unused struct member.
This trick will satisfy GCC because the data arrays are used anyway,
but such data arrays will be dropped from the final binary because
the pointers to them are not used.
Signed-off-by: Masahiro Yamada <[email protected]>
Reported-by: Marek Vasut <[email protected]>
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The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.
Signed-off-by: Simon Glass <[email protected]>
Update to drivers/power/pmic/palmas.c:
Signed-off-by: Keerthy <[email protected]>
Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
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These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.
This applies the following upstream commits by
Thierry Reding <[email protected]> :
604e61e fdt: Add functions to retrieve strings
8702bd1 fdt: Add a function to get the index of a string
2218387 fdt: Add a function to count strings
Signed-off-by: Simon Glass <[email protected]>
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It is not usual that drivers announce when they have been initialized.
use dev_dbg to announce device initialization.
Signed-off-by: Stefan Agner <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL,
the other iomuxc is for SVNS usage, similar with the one in mx7.
Signed-off-by: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Simon Glass <[email protected]>
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This patch add pinctrl driver for rk3399.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Add pin-mux support for UniPhier sLD3 SoC.
Signed-off-by: Masahiro Yamada <[email protected]>
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On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC. Support it for the sLD3 pinctrl driver.
Signed-off-by: Masahiro Yamada <[email protected]>
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These macros are only referenced in pinctrl-uniphier-core.c, so
they need not reside in a header file.
Signed-off-by: Masahiro Yamada <[email protected]>
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This is needed to get access to UniPhier System Bus (external bus).
Signed-off-by: Masahiro Yamada <[email protected]>
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Add a pin controller driver for Meson GXBB adapted from Linux kernel.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Signed-off-by: Beniamino Galvani <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Masahiro Yamada <[email protected]>
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'-' is never used in function names.
Signed-off-by: Masahiro Yamada <[email protected]>
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AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.
Signed-off-by: Wenyou Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Andreas Bießmann <[email protected]>
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