summaryrefslogtreecommitdiff
path: root/drivers/pinctrl
AgeCommit message (Collapse)Author
2023-10-01pinctrl: renesas: Synchronize R8A779G0 V4H PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A779F0 S4 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779F0 S4 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables ↵Marek Vasut
with Linux 6.5.3 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A77951 H3 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A77951 H3 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with ↵Marek Vasut
Linux 6.5.3 Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.5.3Marek Vasut
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levelsMarek Vasut
Currently, the Renesas pin control driver supports pins that can switch their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. However, some SoCs have pins that can switch between 1.8V and 2.5V. Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE capability and voltage level flags by a 2-bit field, to cover three possible I/O voltage switching options. Ported from Linux kernel commit by Geert Uytterhoeven: b88e733ac517 ("pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Drop R8A77950 H3 ES1.x PFC table entryMarek Vasut
Drop outstanding R8A77950 H3 ES1.x PFC table entry from sh_pfc.h . No functional change. Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Rename RZ/A1 R7S72100 PFC tables to RZ/A1Marek Vasut
Rename pfc-r7s72100.c to pfc-rza1.c to match the file name with Linux. Rename the Kconfig symbol to match. No functional change. Signed-off-by: Marek Vasut <[email protected]>
2023-10-01pinctrl: renesas: Rename R8A7795 H3 PFC tables file name to R8A77951Marek Vasut
Rename pfc-r8a7795.c to pfc-r8a77951.c to match the file name with Linux and to indicate the PFC driver does not support R8A77950 H3 ES1.* . No functional change. Signed-off-by: Marek Vasut <[email protected]>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <[email protected]>
2023-09-21pinctrl: zynqmp: Add support for output-enable and bias-high-impedanceAshok Reddy Soma
Add support to handle 'output-enable' and 'bias-high-impedance' configurations in pinctrl driver. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-09-21pinctrl: zynqmp: Add version check for TRISTATE configurationAshok Reddy Soma
Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx ZynqMP Platform Management Firmware) Configuration Param Set version 2.0. If the requested configuration is TRISTATE then check the version before requesting Xilinx firmware to set the configuration. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-08-14pinctrl: rockchip: Fix drive and input schmitt on RK3568Jonas Karlman
On RK3568 most pins have a configurable drive strength of level 0-5 and some pins level 0-11. When rk3568_set_drive is called with a strength value above 7 the drv value written to reg may overflow into the write enable bits, resulting in a bad configuration. This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after drive is configured according to the device tree. Could not get PHY for ethernet@fe010000: addr 0 Level 6-11 can be configured using a second reg for some pins, however the drv value is reused resulting in lower 6 bits being written to reg. Input schmitt is configured in 2-bit fields on RK3568 compared to earlier generation and 2'b10 should be used to enable input schmitt. Change to use regmap_update_bits with a rmask to fix the overflow issue and closer match the linux driver. Bit shift the drv value used for the second reg to configure drive strength level 6-11. Also write correct values for input schmitt setting. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-08-03pinctrl: mediatek: add pinctrl driver for MT7988 SoCWeijie Gao
This patch adds pinctrl and gpio support for MT7988 SoC Signed-off-by: Weijie Gao <[email protected]>
2023-08-03pinctrl: mediatek: add pinmux_set ops supportWeijie Gao
This patch adds pinmux_set ops for mediatek pinctrl framework Signed-off-by: Sam Shih <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2023-08-03pinctrl: mediatek: fix the return value in driving configuration functionsWeijie Gao
The original mediatek pinctrl functions for driving configuration 'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input parameters are not supported. This patch fixes the return value in those functions. Signed-off-by: Sam Shih <[email protected]> Signed-off-by: Weijie Gao <[email protected]>
2023-08-03pinctrl: mediatek: convert most definitions to constWeijie Gao
There exists a situation of the mediatek pinctrl driver that may return wrong pin function value for the pinmux driver: - All pin function arrays are defined without const - Some pin function arrays contain all-zero value, e.g.: static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; - These arrays will be put into .bss section during compilation - .bss section has no "a" attribute and does not exist in the final binary file after objcopy. - FDT binary blob is appended to the u-boot binary, which occupies the .bss section. - During board_f stage, .bss has not been initialized, and contains the data of FDT, which is not full-zero data. - pinctrl driver is initialized in board_f stage, and it will get wrong data if another driver is going to set default pinctrl. Since pinmux information and soc data are only meant to be read-only, thus should be declared as const. This will force all pinctrl data being put into .rodata section. Since .rodata has "a" attribute, even the all-zero data will be allocated and filled with correct value in to u-boot binary. Signed-off-by: Weijie Gao <[email protected]>
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-14pinctrl: nuvoton: fix reset reason error for poweronJim Liu
In non tip mode, BMC first power on with PORST+CORST. the gpio status will error. Signed-off-by: Jim Liu <[email protected]>
2023-07-05Merge tag 'v2023.07-rc6' into nextTom Rini
Prepare v2023.07-rc6
2023-06-29pinctrl: rockchip: Fix Data Abort exception in SPLJonas Karlman
Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers a Data Abort exception from unaligned memory access when the pinctrl driver iterate node properties, e.g. for UART2 on RK3568. setting mux of GPIO0-24 to 1 setting mux of GPIO0-24 to 1 "Synchronous Abort" handler, esr 0x96000021 elr: 000000000000e554 lr : 000000000000e54c x 0: 0000000000000a5c x 1: 0000000000000a5c x 2: 0000000000000007 x 3: 0000000000000065 x 4: 0000000000000007 x 5: 0000000000022d4e x 6: 0000000000000a7c x 7: 00000000000227a4 x 8: 0000000000021cf0 x 9: 0000000000000a7c x10: 0000000000021cf0 x11: 0000000000021cf0 x12: 00000000003fda1c x13: 0000000000000007 x14: 00000000003fd9ec x15: 000000000001c0ff x16: 0000000007000000 x17: 00000000fdccd028 x18: 00000000003fde20 x19: 0000000000000018 x20: 0000000000020670 x21: 0000000000000000 x22: 00000000003fdb00 x23: 00000000003fef90 x24: 0000000000020688 x25: 0000000000000000 x26: 0000000000000001 x27: 00000000003ffc50 x28: 0000000000000000 x29: 00000000003fda60 Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038) Resetting CPU ... Fix this by replacing the loop to access node properties with use of ofnode_for_each_prop instead of the current ifdef. Also continue to next prop instead of aborting at first sign of an unknown property. This fixes the Data Abort exception and also pinconf of e.g. pull and drive in SPL, e.g. for UART2 on RK3568. setting mux of GPIO0-24 to 1 setting mux of GPIO0-24 to 1 setting pull of GPIO0-24 to 5 setting mux of GPIO0-25 to 1 setting mux of GPIO0-25 to 1 setting pull of GPIO0-25 to 5 Fixes: e7ae4cf27a6d ("pinctrl: rockchip: Add common rockchip pinctrl driver") Signed-off-by: Jonas Karlman <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2023-06-28pinctrl: meson: add pinctrl driver for Amlogic A1Igor Prusov
Based on Linux kernel commit: dabad1ff85611 (pinctrl: meson: add pinctrl driver support for Meson-A1 SoC) Signed-off-by: Igor Prusov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini
Signed-off-by: Tom Rini <[email protected]>
2023-06-08pinctrl: renesas: r8a779a0: Remove incorrect AVB[01] pinmux configurationHai Pham
AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array. The latter are correct, hence remove the former. Without this fix, the Ethernet PHY is not operational on the MDIO bus. Ported from Linux kernel commit a145c9a8674ac8fbfa1595276e1b6cbfc5139038 . Signed-off-by: Hai Pham <[email protected]> Signed-off-by: LUU HOAI <[email protected]> Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be --- Cc: Geert Uytterhoeven <[email protected]> Cc: Hai Pham <[email protected]> Cc: LUU HOAI <[email protected]> Cc: Marek Vasut <[email protected]>
2023-06-01pinctrl: nuvoton: set output state before enabling the outputJim Liu
The default output state may be different to request, change the configuration sequence to avoid glitch. Signed-off-by: Jim Liu <[email protected]>
2023-05-31exynos: fix header inclusion guardAndre Przywara
It seems like the header inclusion guard for the Exynos pinctrl header was misspelled. Make the preprocessor symbol for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Stefano Babic <[email protected]>
2023-05-13pinctrl: renesas: add R906G032 driverRalph Siemsen
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC. This is quite rudimentary right now, and only supports applying a default pin configuration as specified by the device tree. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-05-03pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeededDaniel Golle
Commit dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") changed the logic deciding to set R0 and R1 registers for V1 devices. Before: /* Also set PUPD/R0/R1 if the pin has them */ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); if (err != -EINVAL) { mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); } After: /* try pupd_r1_r0 if pullen_pullsel return error */ err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, val); if (err) return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, pullup, val); Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function always either returns 0 in case of success or -EINVAL in case any error has occurred. Hence the logic responsible of the decision to program R0 and R1 has been inverted. This leads to problems on BananaPi R2 (MT7623N) when booting from SDMMC, it turns out accessing eMMC no longer works since U-Boot 2022.07: MT7623> mmc dev 0 Card did not respond to voltage select! : -110 The problem wasn't detected for a long time as both eMMC and SDMMC work fine if they are used to boot from, and hence R0 and R1 were already setup by the bootrom and/or preloader. Fix the logic to restore the originally intended and correct behavior and also change the descriptive comment accordingly. Fixes: dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") Signed-off-by: Daniel Golle <[email protected]> Tested-By: Frank Wunderlich <[email protected]>
2023-04-28pinctrl: sunxi: Add NAND pinmuxesSamuel Holland
NAND is always at function 2 on port C. Pin lists and mux values were taken from the Linux drivers. Reviewed-by: Andre Przywara <[email protected]> Reviewed-by: Jagan Teki <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-21pinctrl: rockchip: Fix IO mux selection on RK3568Jonas Karlman
IO mux selection is not working correctly for all pins. Sync mux route data from linux to add any missing and update wrong trigger pins to fix this. Also apply the pull-up fix needed for GPIO0 D3-D6. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <[email protected]>
2023-04-21pinctrl: rockchip: support rk3588 pinctrlJianqun Xu
Add support for Rockchip rk3588 variant of pinctrl. The driver is adapted from the Linux driver. Signed-off-by: Jianqun Xu <[email protected]> [[email protected]: port to latest U-boot, bring more changes from Linux use translated pull values table] Signed-off-by: Eugen Hristev <[email protected]> Reviewed-by: Kever Yang <[email protected]> Tested-by: Jonas Karlman <[email protected]> Reviewed-by: Jonas Karlman <[email protected]>
2023-04-20pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Jianlong Huang <[email protected]> Signed-off-by: Yanhong Wang <[email protected]> Tested-by: Conor Dooley <[email protected]>
2023-04-19pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()Patrice Chotard
For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]>
2023-04-07pinctrl: renesas: Add R8A779G0 V4H PFC tablesHai Pham
Add pinctrl tables for R8A779G0 V4H SoC. Based on Linux next 20230228 PFC tables tables up to commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: LUU HOAI <[email protected]> Signed-off-by: Hai Pham <[email protected]> Signed-off-by: Takeshi Kihara <[email protected]> Signed-off-by: Phong Hoang <[email protected]> Signed-off-by: Marek Vasut <[email protected]> [Marek: Sync with Linux next 20230228, sort sh_pfc_pinconf_set voltage args]
2023-04-07pinctrl: renesas: Add R8A779F0 S4 PFC tablesLUU HOAI
Add pinctrl tables for R8A779F0 S4 SoC. Based on Linux next 20230228 PFC tables tables up to commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: LUU HOAI <[email protected]> Signed-off-by: Hai Pham <[email protected]> Signed-off-by: Marek Vasut <[email protected]> [Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
2023-04-03pinctrl: fix pinctrl_gpio_get_pinctrl_and_offset for gpio-ranges arrayQuanyang Wang
Sometimes a multi-element array is used for "gpio-ranges" property in dts file: qe_pio_e: gpio-controller@1460 { ...... gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; ...... }; But the function pinctrl_gpio_get_pinctrl_and_offset can't handle this case because the "index" argument passed to dev_read_phandle_with_args is fixed to be "0". Use a loop to traverse the array to fix it. Signed-off-by: Quanyang Wang <[email protected]>
2023-03-10pinctrl: renesas: Drop non-existent PFC info table entriesMarek Vasut
Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut <[email protected]>
2023-03-01arm64: a37xx: pinctrl: probe after bindingRobert Marko
Currently, pinctrl drivers are getting probed during post-bind, however that is being reverted, and on A37XX pinctrl driver is the one that registers the GPIO driver during the probe. So, if the pinctrl driver doesn't get probed GPIO-s won't get registered and thus they cannot be used. This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s and without them being registered networking won't work as it only has one SFP slot and the TX disable GPIO is on the SB controller. So, lets just add a flag only to A37XX driver to probe after binding in order for the GPIO driver to always get registered. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Simon Glass <[email protected]>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-30 04:30:26 +0000