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Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Ported from the Mediatek SDK. The upstream Linux kernel also has the
same register map as the SDK.
Signed-off-by: Shiji Yang <[email protected]>
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David Lechner <[email protected]> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/[email protected]
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Add pinctrl support for MT8365 SoC.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Vitor Sato Eschholz <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <[email protected]>
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Tom Rini <[email protected]> says:
As seen by a number of patches fixing memory leaks, U-Boot has a problem
with developer expectations around devm_kmalloc and friends. Namely,
whereas in Linux these memory allocations will be freed automatically in
most cases, in U-Boot this is only true if DEVRES is enabled. Now,
intentionally, in xPL phases, we do not (and do not offer as an option)
enabling DEVRES. However in full U-Boot this is left either to the user,
or some drivers have select'd DEVRES on their own. This inconsistency is
a problem. This series goes and deals with two small issues that were
shown by having all drivers that use devm_.alloc to allocate memory also
select DEVRES and then we make DEVRES no longer be a prompted option and
instead select'd as needed. We do not make this unconditional as it
would result in growing the resulting binary on the many platforms which
have no users of the devm_.alloc family of functions.
Link: https://lore.kernel.org/r/[email protected]
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Jim Liu <[email protected]> says:
Modify npcm7xx/8xx features and bug fixes.
Link: https://lore.kernel.org/r/[email protected]
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Fix typos in the pin name of GPIO191 and GPIO192
Signed-off-by: Stanley Chu <[email protected]>
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smb11ddcm: connect SMB11 to external DDC pins
smb11ddcs: connect SMB11 to internal GFXDDC
Signed-off-by: Stanley Chu <[email protected]>
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If func->pins could not be allocated, one must also free
func variable that was allocated previously.
Signed-off-by: Francois Berder <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
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- Assorted updates
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This patch adds support for configuring GPIO pull-up and pull-down
resistors in the BCM283x pinctrl driver. It implements the brcm,pull
device tree property to control pin bias settings.
The implementation follows the hardware-specific pull control
mechanisms:
- BCM2835: two-step GPPUD register sequence
- BCM2711: direct per-pin control registers
This enables device tree configurations to specify pull-up, pull-down,
or no bias for individual GPIO pins.
Tested on Raspberry Pi boards with both BCM2835 and BCM2711 SoCs.
Signed-off-by: Cibil Pankiras <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
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Rev.0.81 of the R-Car V4M Series Hardware User’s Manual removed the
"STPWT_EXTFXR" signal from the pin control register tables. As this is
further unused in the pin control driver, it can be removed safely.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Rev.0.71 of the R-Car V4M Series Hardware User’s Manual removed the
"CC5_OSCOUT" signal from the pin control register tables. As this is
further unused in the pin control driver, it can be removed safely.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"STPWT_EXTFXR" signal from the pin control register tables. As this is
further unused in the pin control driver, it can be removed safely.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"CC5_OSCOUT" signal from the pin control register tables. As this is
further unused in the pin control driver, it can be removed safely.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the
"AVB[01]_MII_*" signals from the pin control register tables. As these
are further unused in the pin control driver, they can be removed
safely.
Signed-off-by: Thanh Quan <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The pinctrl blocks for Exynos7870 and Exynos7880 are similar, however in
Exynos7870, the CCORE block is actually referred to as MIF. Since
ordering happens lexically, it isn't directly compatible with
samsung,exynos78x0-pinctrl.
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The devicetree of Samsung devices typically have the pin controller and
GPIO bank descriptors under the same pinctrl node. In U-Boot, these are
handled by two separate drivers. It is not possible to invoke both
drivers from a single node compatible.
Bind the GPIO driver on pinctrl driver bind, with the same OF node as
the pinctrl driver. This solution is already being used in other pinctrl
drivers. The hierarchy, as represented in `dm tree`, is as follows:
pinctrl@13750000
|-- gpio-banks
| |-- gpr0-gpio-bank
| |-- gpr1-gpio-bank
| |-- gpr2-gpio-bank
| |-- gpr3-gpio-bank
| `-- gpr4-gpio-bank
|-- sd0-bus-width1-pins
|-- sd0-bus-width4-pins
|-- sd0-bus-width8-pins
`-- sd0-clk-pins
Since a bind function doesn't exist, create and add it to all pinctrl
drivers.
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Add initial pin control tables for the Renesas R-Car X5H R8A78000 SoC.
This SoC is the first one which includes custom DRV register handling,
different from previous generations due to change in DRV register bit
layout.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Khanh Le <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The upcoming Renesas R-Car Gen5 uses different mapping of bits in DRV
control register, which is incompatible with existing DRV register bit
mapping. Add .set_drive_strength callback into sh_pfc_soc_operations
and call it from sh_pfc_pinconf_set(), to allow each SoC specific PFC
driver to implement replacement .set_drive_strength. Make the current
sh_pfc_pinconf_set_drive_strength() non-static, rename it with rcar_
prefix, and pass it as .set_drive_strength for existing PFC drivers.
This is a preparatory patch for R-Car Gen5, no functional change.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
[Marek: Consistently use .set_drive_strength() and pass exisiting
sh_pfc_pinconf_set_drive_strength() as its parameter for
all PFC drivers. Rewrite commit message.]
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Show bit position in config write debug log, which is helpful for cases
where the p port setting is applied at the exact p bit position.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Unsplit the string
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Fix Kconfig entry indent to be always consistently indented with
leading tabs, never with leading spaces. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Signed-off-by: Danila Tikhonov <[email protected]>
Co-developed-by: Jens Reidel <[email protected]>
Signed-off-by: Jens Reidel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6350 SoC, with support for special pins.
Correct pin configuration is required for working debug UART and eMMC/SD
cards.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
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There's no WEST, SOUTH or NORTH in sc7280 pinctrl. Fix the offset of the
ufs_reset pin.
Fixes: 51ec7fdb64b ("pinctrl: qcom: add sc7280 pinctrl driver")
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add a pinctrl driver for the TLMM block found in the SDM670 SoC.
Signed-off-by: David Wronek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.
The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.
Signed-off-by: Naman Trivedi <[email protected]>
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Acked-by: Senthil Nathan Thangaraj <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
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meson_gpio_get() always assumes gpio is configured to input mode. This
is incorrect and breaks `gpio toggle` command:
gpio: pin aobus-banks2 (gpio 2) value is 0
Warning: value of pin is still 1
Fix it by adding the logic to handle both input and output mode.
Fixes: 2009a8d03fe5 ("pinctrl: meson: add GPIO support")
Signed-off-by: Yang Xiwen <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Define the daisy register offset for i.MX94 at 0x608 within the iomuxc
register space. This enables correct pad selection for daisy chain
configuration on i.MX94 platforms.
Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
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It's common that UARTs are bound and probed before U-Boot relocation, in
which case the UART's pincontroller and pinconfig must be probed first.
Let's apply DM_FLAG_PRE_RELOC to the driver, allow it to bind before
relocation.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Prepare v2025.10-rc4
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In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Prepare v2025.10-rc3
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In zynqmp_pinconf_set if param is PIN_CFG_IOSTANDARD or
PIN_CONFIG_POWER_SOURCE and zynqmp_pm_pinctrl_get_config returns an
error then value will not be assigned to when its value is tested to be
not equal to arg. Add code to only test value not equal to arg if ret is
false.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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In zynqmp_pinctrl_prepare_func_groups if called with func->ngroups == 0
then ret will not be assigned to before its value is returned on exit.
Initialise ret to ensure it is always valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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In s5pxx18_pinctrl_set_state testing count to be negative will always
fail as count is unsigned despite receiving the return value of a
function that returns an int. Change count and idx to be of type int to
allow the test to work as expected and remove the need for any implicit
casts. Also change pin to be u32 which is what all called functions
expect.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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Add pinmux for the VCD input to use the HSYNC signal.
Signed-off-by: Stanley Chu <[email protected]>
Signed-off-by: Jim Liu <[email protected]>
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In stmfx_read_reg there is duplicated code to detect ret < 0 and return
ret if so. Remove one version of it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In single_read there is a switch block with a default label. All cases
in the switch block, including the default, return directly. So any code
following the switch block is unreachable. Remove the unreachable code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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A few pinctrl drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364
Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
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The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The Linux pinctrl-sx150 was originally written as a GPIO driver
and fully rewritten by me as a Pinctrl driver and extended by
other contributors.
Fixup the Copyright header style and correctly report the
Copyright headers from the Linux driver.
Signed-off-by: Neil Armstrong <[email protected]>
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Fixes: 5451504256d3 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver")
Signed-off-by: Chali Anis <[email protected]>
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The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <[email protected]>
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