| Age | Commit message (Collapse) | Author |
|---|
|
The first AM6x device was the AM654x, but being the first we named it
just AM6, since more devices have come out with this same prefix we
should switch it to the normal convention of using the full name of the
first compatibility device the series. This makes what device we are
talking about more clear and matches all the K3 devices added since.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Tighten up symbol dependencies in a number of places. Ensure that a TPL
specific option has at least a direct dependency on TPL. In places
where it's clear that we depend on something more specific, use that
dependency instead.
Reported-by: Pali Rohár <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
AM625 is the first device of the family. Add DT bindings for the same.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Gowtham Tammana <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Add support for DDR subsystem in J721S2 SoC.
Signed-off-by: David Huang <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
|
|
Introduce support for the AM64 DDRSS controller which uses the 16bit
variation of the controller. This controller shares much functionality
with the existing J721e support, so this patch introduces only the new
code needed for am64 specific support from "_16bit_" files with headers
under "16bit/" include path/.
Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use
with CONFIG_K3_DDRSS to allow selecting AM64 support.
Signed-off-by: Dave Gerlach <[email protected]>
|
|
Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.
Signed-off-by: Dave Gerlach <[email protected]>
|
|
the aspeed ddr sdram controller needs to know if the memory chip mounted on
the board is dual x8 die or not. Or it may get the wrong size of the
memory space.
Signed-off-by: Dylan Hung <[email protected]>
Reviewed-by: Ryan Chen <[email protected]>
|
|
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.
Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.
Signed-off-by: Aaron Williams <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
|
|
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <[email protected]>
Tested-by: Bin Meng <[email protected]>
|
|
Add SDRAM driver for i.MXRT SoCs.
Signed-off-by: Giulio Benetti <[email protected]>
|
|
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
|
|
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <[email protected]
Signed-off-by: Lokesh Vutla <[email protected]>
|
|
Right now sdram drivers in rockchip SoC are built based
on the SoC configs which may not be an adequate solutions
while adding common or debug driver.
So, add meaningful Kconfig options start with rk3399.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Schuyler Patton <[email protected]>
Signed-off-by: James Doublesin <[email protected]>
|
|
Add a RAM driver for the MPC83xx architecture.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Mario Six <[email protected]>
|
|
Add driver and binding for stm32mp1 ddr controller and phy
Signed-off-by: Patrick Delaunay <[email protected]>
|
|
Signed-off-by: Jagan Teki <[email protected]>
|
|
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
Signed-off-by: Philipp Tomsich <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
Signed-off-by: Vikas Manocha <[email protected]>
cc: Christophe KERELLO <[email protected]>
|
|
Signed-off-by: Masahiro Yamada <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <[email protected]>
|
